Samsung Electronics Co., Ltd.

Hyun Su Chea

Sang-Ho Kim

Soomin Lee

Sodam Ju

Jahoon Jin

Kyunghwan Min

Jihoon Lim

A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n−1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n−1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n−1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n−1 first signals transitions from the second signal level to the first signal level, to output n−1 second signals.

Growing community of inventors

Seoul, South Korea

Hyun Su Chea