Samsung Electronics Co., Ltd.

Hyun-Soon Jang

Ho-cheol Lee

Si-Yeol Lee

Churoo Park

Myung-Ho Kim

Chull-Soo Kim

Seung-Hun Lee

Yun-Ho Choi

Tae-jin Kim

Jong-hyun Choi

Dong-Ho Lee

Byung-Se So

Hyong-Ryol Hwang

Jei-Hwan Yoo

Woo-Seop Jeong

Jae-yoon Sim

Seung-whan Seo

Jong-eon Lee

Jong-Hyun Choi

Chang-Hyun Kim

Kyu-Hyoun Kim

Kyung-Ho Kim

Sang-kil Lee

Kyung-ho Kim

Dong-Il Seo

Seung-hun Lee

Woo-seop Jeong

Hong-Beom Kim

Kwun-soo Cheon

Jae-hoon Kim

Jae-sung Kang

Kyoung-Hwan Kwon

Eun-sung Seo

Bok-Gue Park

Il-Jae Cho

Byung-heon Kwak

Sang-Joon Ryu

Yong-hwan Cho

Hyun-tae Lim

A method of testing a semiconductor memory device includes writing first data to a memory cell array in the semiconductor memory device, loading second data from the memory cell array onto a plurality of data pads of the semiconductor memory device, rewriting the second data to the memory cell array, and outputting test result data through one or more test pads. The first data is received from an external device through the one or more test pads, which correspond to one or more of the plurality of data pads. The test result data is based on the rewritten data in the memory cell array.

Method of testing a semiconductor memory device

A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

Parallel bit test apparatus and parallel bit test method capable of reducing test time

Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

Multi-chip package for reducing parasitic load of pin

Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.

Semiconductor memory device including post package repair control circuit and post package repair method

A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.

Memory using packet controller and memory

A fuse bank of a semiconductor memory device is provided. The fuse bank includes first and second laser fuses. The first laser fuse includes a first laser fusing region disposed in a first direction, a first connecting line region bent in a second direction, and a second connecting line region bent in a third direction. The second laser fuse includes a second laser fusing region disposed in the first direction, a third connecting line region bent in the second direction, and a fourth connecting line region bent in the third direction. The first laser fuse and the second laser fuse have a space of a predetermined distance there between. The first and second laser fusing regions form a laser fusing region of the fuse bank, and the first and second laser fuse are disposed on a plane. The fuse bank is embodied on a single layer.

Layout structure of fuse bank of semiconductor memory device

A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal from a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other.

Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., &#xbd; &#xbc;, &#x215b;, or 1/16) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

System and method for performing partial array self-refresh operation in a semiconductor memory device

In a frequency multiplier and a method of multiplying a frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer, the frequency multiplier receives an external clock signal having a predetermined frequency and outputs an internal clock signal having greater frequency than the predetermined frequency. In the semiconductor device, the data output buffer outputs data tested in response to test data. Therefore, it is possible to test a plurality of memory cells at a time by using a clock signal having a low frequency. In addition, the time and cost required for the test can be greatly reduced, and conventional testing equipment that operates at a relatively low frequency can be effectively used.

Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method

Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., &frac12; &frac14;, &frac18;, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

A semiconductor memory device which provides an improved operation performance in response to a relatively low external power voltage is included. The device comprises a plurality of direct-current voltage generating circuits for generating a plurality of direct-current voltages and a plurality of reference voltage generating circuits for generating reference voltages for the plurality of the direct-current voltage generating circuits, respectively.

Semiconductor memory device and voltage generating method thereof

A semiconductor device is provided for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory comprising; a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and biasing circuitry for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to prevent false triggering of circuits upon entry/exit of DPD mode. Also provided is a semiconductor device, comprising: a plurality of input buffers for buffering a plurality of DPD-type signals for signaling a power down (DPD) condition including a DPD enter/exit signal: an auxiliary buffer for separately buffering the DPD enter/exit signal; a plurality of voltage generators for supplying operating voltages to internal circuit; DPD control circuit for receiving the DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators when DPD enter command is decoded, and to turn off the plurality of buffers excluding the auxiliary buffer; and an auto-pulse generator for generating a voltage pulse upon receiving the DPD exit command to initialize internal circuits of the semiconductor device.

Power down voltage control method and apparatus

A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

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Seoul, South Korea

Hyun-Soon Jang