Samsung Electronics Co., Ltd.

Hyun-sik Kim

Sang-mock Lee

Eun-Sung Lee

Heon-Jong Shin

Kyu-hyoung Lee

Xiangshu Li

Hang-jae Yu

A thermoelectric material including: a bismuth-tellurium (Bi&#x2014;Te)-based thermoelectric material matrix; and a nano-metal component distributed in the Bi&#x2014;Te-based thermoelectric material matrix, wherein a Lotgering degree of orientation in a c-axis direction is about 0.9 to about 1.

Thermoelectric material and method of preparing the same

A scheduling method implemented in an operating system kernel for supporting multimedia applications is provided. The micro-scheduling method includes the steps of determining a performance parameter by measuring I/O-bound job performance and CPU-bound job performance in a given application, and appropriately adjusting the performance parameter according to a policy set by a system administrator when carrying out job admission control. Determining an order of priority for processing application classes based on the performance measuring and job admission control by scheduling the periodical execution of I/O jobs of data which need not be moved to a user space due to the characteristics of multimedia applications, and executing a special I/O system call according to the order of priority for processing is also provided. The micro-scheduling method enables the support of accurate QoS for any operating system which supports multimedia applications.

Micro-scheduling method and operating system kernel

Heavily doped source/drain regions are formed in an integrated circuit substrate prior to forming lightly doped source/drain regions in the integrated circuit substrate. High temperature thermal processing preferably is carried out prior to forming the lightly doped source/drain regions in the integrated circuit substrate. Reduced short channel effects may thereby be obtained while still achieving shallow junctions. More specifically, an insulated gate electrode comprising polysilicon is formed on an integrated circuit substrate. The insulated gate electrode is oxidized. A gate spacer is formed on the oxidized sidewalls of the insulated gate electrode. Heavily doped source/drain regions are formed in the integrated circuit substrate by first implanting ions into the integrated circuit substrate using the insulated gate electrode and the gate spacer on the oxidized sidewalls of the insulated gate electrode as an implantation mask. The gate spacer is removed from the oxidized sidewalls of the insulated gate electrode after performing the step of forming heavily doped source/drain regions in the integrated circuit substrate. Finally, lightly doped source/drain regions, that are lightly doped relative to the heavily doped source/drain regions, are formed in the integrated circuit substrate. The lightly doped source/drain regions are formed by implanting ions into the integrated circuit substrate using the insulated gate electrode as an implantation mask, after performing the step of removing the gate spacers from the oxidized sidewalls of the insulated gate electrode.

Methods of fabricating field effect transistors by first forming heavily doped source/drain regions and then forming lightly doped source/drain regions

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Gyeonggi-do, South Korea

Hyun-sik Kim