Skhynix Inc.

Hynix Semiconductor Inc.

Hyun Seung Yoo

Eun Seok Choi

Se Jun Kim

Kyoung Hwan Park

Hee Youl Lee

Ki Hong Lee

Jung Ryul Ahn

Sung Wook Jung

Keon Soo Shim

Yu Jin Park

Moon Sik Seo

Ki Seon Park

Dong Kee Lee

Young Ok Hong

Won Sic Woo

Moon Sig Joo

Myung Shik Lee

Kyung Pil Hwang

Yong Top Kim

Jae Young Park

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit for applying a program voltage and verifying whether a program of the memory cell array has been completed, and a control logic for controlling the peripheral circuit to apply an increased program voltage to the memory cell array while applying a reprogram permission voltage to a bit line coupled to the memory cells that previously passed a program verification but has failed a program re-verification.

Semiconductor memory device and operating method thereof

A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.

Semiconductor device, semiconductor system having the same and operating method thereof

A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality of normal memory cells, a select transistor, and a dummy memory cell. The semiconductor memory device may include a voltage generator configured for generating a program voltage applied to a normal memory cell selected among the plurality of normal memory cells, and for generating a dummy word line voltage applied to the dummy memory cell in a program operation. The semiconductor memory device may include a control logic configured for controlling the voltage generator to adjust the dummy word line voltage based on the program voltage.

Semiconductor memory device including a dummy memory cell and method of programming the same

A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.

Semiconductor memory apparatus and method for reading data from the same

A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kmemory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, 'k' denotes an integer that is equal to or greater than '2'.

Memory string and semiconductor device including the same

A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.

3-D nonvolatile memory device and method of manufacturing the same

A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.

Non-volatile memory device and method of manufacturing the same

A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.

Nonvolatile memory device and method of fabricating the same

A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.

Growing community of inventors

Icheon-si, South Korea

Hyun Seung Yoo