Samsung Electronics Co., Ltd.

Hyun-Seung Song

Hwi-Chan Jun

Dong-Hyun Kim

Heonjong Shin

Jonghyun Lee

Jae-Jik Baek

Doohyun Lee

Yongsik Jeong

Tae-Yeol Kim

Hyeonuk Kim

Sora You

Seung-Seok Ha

Kwang-Young Lee

Yeongchang Roh

Kyoung-Mi Park

Jongun Kim

Dong Il Bae

Hyo-Jin Kim

Sang-hyun Lee

Dae Won Ha

Beomjin Park

Kyung-Eun Kim

Seung Seok Ha

Hyun-Jung Lee

Joon-Seok Moon

Jae-Rok Kahng

Dong-Soo Woo

Keon Yong Cheon

Sangwon Baek

Deok-han Bae

Jong-Un Kim

Noh Yeong Park

Jae-Kyun Park

A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

Semiconductor devices and methods of fabricating the same

A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.

Method of fabricating semiconductor devices including a fin field effect transistor

A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.

Semiconductor device

A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.

Method of fabricating semiconductor device

Semiconductor devices inlcluding a fin field effect transistor

A semiconductor device includes a first impurity region, a channel pattern, a second impurity region, a gate structure, a first contact pattern, a second contact pattern and a spacer. The first impurity region may be formed on a substrate. The channel pattern may protrude from an upper surface of the substrate. The second impurity region may be formed on the channel pattern. The gate structure may be formed on a sidewall of the channel pattern and the substrate adjacent to the channel pattern, and the gate structure may include a gate insulation pattern and a gate electrode. The first contact pattern may contact an upper surface of the second impurity region. The second contact pattern may contact a surface of the gate electrode. The spacer may be formed between the first and second contact patterns. The spacer may surround a portion of a sidewall of the second contact pattern, and the spacer may contact a sidewall of each of the first and second contact patterns.

Semiconductor device and method of fabricating the same

A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.

A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction. The second sub-contact is connected to the first sub-contacts and is in contact with a top surface of the first gate electrode. In the first direction, each of the first sub-contacts has a first width and the second sub-contact has a second width smaller than the first width.

Semiconductor device and method of manufacturing the same

Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion.

Method for manufacturing semiconductor device using gate portion as etch mask

Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

Semiconductor device having a resistor structure

A semiconductor device includes a fin portion protruding from a substrate. The fin portion includes a base part, an intermediate part on the base part, and a channel part on the intermediate part. A width of the intermediate part is less than a width of the base part and greater than a width of the channel part. A gate electrode coves both sidewalls and a top surface of the channel part, and a device isolation pattern covers both sidewalls of the base part and both sidewalls of the intermediate part.

Semiconductor device including field effect transistor

Method of fabricating semiconductor device having a resistor structure

Growing community of inventors

Incheon, South Korea

Hyun-Seung Song