Skhynix Inc.

Hyun Seung Kim

Young Jun Yoon

Seung Wook Oh

Hyeong Soo Jeong

Noh Hyup Kwak

Min Gu Kang

Sang Sic Yoon

Ho Uk Song

Kyong Ha Lee

Duck Hwa Hong

Jin Youp Cha

Tae Kyun Shin

Yu Ri Lim

Ju Hyuck Kim

Min Jun Choi

Yong Ho Seo

Jin Suk Oh

A semiconductor device includes a read circuit configured to latch read parity including error information on read data output from a memory circuit to generate latch parity when a test read control signal is enabled. The semiconductor device also includes a parity selection circuit configured to output the latch parity as parity when a test selection signal is enabled. The semiconductor device further includes a write circuit configured to receive write data generated from data and the parity, and to correct error of the write data, based on write parity including error information on the write data and the parity to generate correction data when a test write control signal is enabled.

Semiconductor devices for detecting defects in error correction circuits, and methods of performing test mode operations

A semiconductor device includes a strobing signal generating circuit configured to sequentially generate write input signals, based on a write strobing signal and to sequentially generate write output signals, based on a delayed write strobing signal when a write operation is performed. The semiconductor device incudes an input/output control circuit configured to receive and latch write data input from a data input/output circuit, based on the write input signals, and to store the latched write data in a cell area as write core data, based on the write output signals.

Semiconductor devices related to data input and output operations

A semiconductor device includes a first crack detection circuit configured to receive a first external detection signal and output the first external detection signal as a first internal detection signal through a first metal line or configured to receive the first internal detection signal through the first metal line and output the first internal detection signal as the first external detection signal, and a second crack detection circuit configured to receive the first internal detection signal and output the first internal detection signal as a second internal detection signal through a second metal line or configured to receive the second internal detection signal through the second metal line and output the second internal detection signal as the first internal detection signal.

Semiconductor device and method for performing crack detection operation

According to an embodiment of the present disclosure, a semiconductor device includes an even data input circuit configured to store, in an even core cell, data that is input through an even data pad and that has a first pattern in response to an even data input strobe signal in a write operation of a parallel test. The semiconductor device includes an odd data input circuit configured to store, in an odd core cell, data that is input through the even data pad and that has a second pattern in response to an odd data input strobe signal in the write operation of the parallel test.

Semiconductor device related to a parallel test

A semiconductor device includes first and second memory devices configured to share a first transmission line from which a write clock is received and a second transmission line from which data is received. The memory devices receive the data through first to eighth internal clocks that are generated by dividing a frequency of the write clock, and selectively align and store at least some of the data that is received in synchronization with the first to eighth internal clocks based on timing at which the data is synchronized with the write clock.

Semiconductor system for performing a data alignment operation

A semiconductor device includes an input control signal generation circuit configured to generate an input control signal when performing an internal operation and configured to adjust a time point at which the input control signal is generated, based on whether a frequency of a clock corresponds to a preset frequency range. The semiconductor device includes an output control signal generation circuit configured to generate an output control signal after a latency elapses when performing the internal operation. The semiconductor device includes a pipe latch circuit configured to latch input data based on the input control signal and configured to output the latched input data as output data based on the output control signal.

Semiconductor device including pipe latch circuit

A semiconductor device includes a pre-pulse generation circuit configured to generate a pre-pulse, based on a write shifting pulse and a write leveling activation signal; a write control signal generation circuit configured to generate a write control signal, based on the pre-pulse and a division clock; and a write leveling control circuit configured to generate detection data including information on a phase difference between a data clock and a system clock, based on the pre-pulse and the division clock.

Semiconductor device and semiconductor system related to write leveling operations

A semiconductor device includes an output control circuit configured to generate a pre-output control signal and an output control signal according to the number of times that an output strobe pulse is inputted. The semiconductor device also includes a pipe circuit configured to generate latched data by latching input data on the basis of an input control signal, select some bits of the bits of the latched data and set the selected bits to pre-output data on the basis of the pre-output control signal, and output the pre-output data as output data on the basis of the output control signal.

Semiconductor device using pipe circuit

An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

Electronic device for adjusting refresh operation period

A memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data.

Memory device and memory system controlling generation of data strobe signal based on executing a test

An electronic device includes a masking signal generation circuit configured to generate a test masking signal by receiving a fuse data during a period in which a test masking mode is executed; and a test mode signal generation circuit configured to, when a test command for executing a test in an internal circuit is input, execute the test based on the test masking signal.

Electronic device for executing test

An electronic device includes a controller and a semiconductor device. The controller outputs a clock signal and a command signal having a first setting combination or a second setting combination and receives a temperature information signal. The semiconductor device compares an input time of a latch signal generated based on the command signal having the first setting combination with an input time of a temperature output control signal generated internally. In addition, the semiconductor device updates a temperature code according a comparison result of the input times of the temperature output control signal and the latch signal to generate the temperature information signal.

Electronic devices performing temperature information update operation

An electronic device includes a pattern data generation circuit and a data input/output (I/O) circuit. The pattern data generation circuit generates pattern data having a serial pattern based on a command/address signal. The data I/O circuit outputs the pattern data or read data as internal data based on a read command for a read operation and an internal command in a test mode. The data I/O circuit receives and stores the internal data, which are output, as write data for a write operation.

Electronic devices including a test circuit and methods of operating the electronic devices

A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.

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Icheon-si, South Korea

Hyun Seung Kim