Samsung Electronics Co., Ltd.

Hyun-seop Shim

Jun-Ho Lee

Jeong-ho Bang

Jae-il Lee

Ki-Sang Kang

Do-young Kam

Ju-il Kang

Seong-goo Kang

Dong-wook Kim

Hyuk Jae Kwon

Hyo-geun Chae

Byoung-jun Min

Jong-bok Tcho

Ja-hyun Koo

Keun-won Cho

A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.

Multifunctional handler system for electrical testing of semiconductor devices

A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.

Handlers for testing semiconductor devices that are capable of maintaining stable temperature in test environments

A test kit for a semiconductor package and a method for testing the semiconductor package using the same are provided. The test kit for a semiconductor package includes a pick-and-place tool for picking up and loading/unloading the semiconductor package, a head assembly having a package guider and a socket guider, and a socket which is positioned under the head assembly. The socket guider performs a pre-alignment function for a correct operation of the package guider, before the package guider starts operating. The package guider aligns the semiconductor package.

Test kit for semiconductor package and method for testing semiconductor package using the same

When high speed memory devices are tested using a tester having a lower operating frequency than the operational speed of the memory device, limit conditions for the tester signals are required to prevent the interference between the tester and device signals. The present invention provides the limit conditions for the shift and strobe signal. The strobe signal is delivered to comparators with a delivery delay time defining the dead time zone. The shift signal controls the data path of the device to and from a driver and a comparator. When the strobe signal is within the present test cycle, the shift signal of a read cycle must be activated at the same time or earlier than the activation time of the WE/ signal of the next write cycle and the shift signal of a write cycle must start at the same time or earlier than the activation time of the OE/ signal of the next read cycle. When the strobe signal is outside of the test cycle, the shift signal must meet prescribed maximum and minimum timing conditions.

Test method for high speed memory devices in which limit conditions for the clock are defined

A test method can test high speed synchronous memory devices by using a tester having a minimum rate and a minimum clock cycle slower than operating speed of the devices to be tested. The test method transforms a pulse signal generated by the tester to be transformed into a clock signal having a frequency higher than the minimum rate, a test cycle of the test equipment then being determined based on a cycle time of the pulse signal, the operating cycle of the IC devices being determined based on a cycle time of the clock signal, and an input setup time and an input hold time of control signals which are supplied from the tester to the devices are separately measured for every two or more operating cycles of the IC devices.

Test method of integrated circuit devices by using a dual edge clock

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Incheon, South Korea

Hyun-seop Shim