Samsung Electronics Co., Ltd.

Kongju National University Industry-university Cooperation Foundation

Hyun-sang Park

Si-hwa Lee

Do-Hyung Kim

Doo-hyun Kim

Sun-young Shin

Young-su Moon

Do-hyung Kim

Young-sam Shin

Won-Jong Lee

Jae-don Lee

Suk-ki Yoon

Tae-hwan Park

Sun-Young Shin

Jung-hee Choi

An image processing apparatus and a method are provided. The image processing apparatus includes an accumulator for accumulating image data in which images are accumulated when the images are input from an image sensor, a memory for storing the pieces of image data that are output from the accumulator, and a processor for generating a final image using at least one image data from among the pieces of image data that are stored in the memory.

Method and apparatus for processing image according to image conditions

A pipeline system includes input buffers, a relay for controlling withdrawal of data stored in the input buffers, and functional blocks for performing one or more processing operations. A method of operating a pipeline system includes withdrawing data from one of input buffers and performing different one or more processing operations.

Pipeline system including feedback routes and method of operating the same

Provided are a method and apparatus for buffering image data for motion compensation. One of two buffers of a double register array buffer, i.e., a first buffer, is selected as a buffer in which data corresponding to a row of a block of an image is to be written and the other of the double register array buffer is selected as a buffer from which data corresponding to another row of the block is to be read, thereby speeding up motion compensation processing when compared with the use of a single register array buffer.

Double register array buffer for motion compensation

Provided are a method and apparatus for compensating motion of a moving image. The method includes calculating a pixel value of a pixel located between pixels of a reference image corresponding to a current image based on pixel values of the pixels of the reference image by using at least one method from among a plurality of methods, such as a vertical linear filtering, a horizontal linear filtering, and a cubic filtering, of interpolating the pixels of the reference image according to codec information indicating one of a plurality of codecs, such as MPEG4, H.264/AVC, and VC1, and restoring the current image by adding motion compensation data, including the calculated pixel value, and a difference between the reference image and the current image.

Method and apparatus for motion compensation supporting multicodec

An image compression method adapted to determine block mode for an input image and a related circuit are disclosed. First and second determinations of block mode are made in relation to first and second threshold comparisons. The second comparison is conditioned upon a prior determination of auto-exposure control for the input image.

Method and circuit for coding mode determinations recognizing auto exposure control of input image

Provided are a moving picture encoding apparatus having an increased encoding speed, and a method thereof, where the moving picture encoding apparatus includes a first frame memory storing an input image divided into brightness blocks of current macroblocks, each stored in one page; a second frame memory storing a previous image divided into clusters, each including brightness blocks of a predetermined number of macroblocks and being stored in one page; a motion estimation processor reading a brightness block of a current macroblock from the first frame memory, reading a cluster corresponding to a search area of the current macroblock from a search area of the second frame memory, and calculating a motion vector of the brightness block of the current macroblock on the basis of the read brightness block of the current macroblock and the read cluster; and a motion compensation processor reading a brightness block of a macroblock, which is moved by reflecting the motion vector on the current macroblock, from the second frame memory.

Moving picture encoding apparatus having increased encoding speed and method thereof

An image processing apparatus for converting image data between a raster format and a block format including an image data processor for providing the image data including a luminance component and at least one chrominance component in the raster format, at least two FIFO memories for storing corresponding image data components, a multiplexer for multiplexing the image data components from the at least two FIFO memories, a line buffer memory for storing outputs of the multiplexer linearly, and an image compressor for receiving the image data components in block format in sequence from the unified line buffer memory and compressing the received image data components. The image processing apparatus may also include an address generator for generating a common read/write address for the line buffer memory; and an image compressor for receiving image data of a v*h block unit from the line memory and compressing the received image data, where when the image data of v lines are read out from the line memory in a block scan order referring to the common read/write address, next image data of v lines are written into the single line memory with reference to the same common read/write address.

Image processing apparatus and method

A self-generated strobe signal generator generates a self-generated strobe signal for a peripheral device using a peripheral device selection signal and a clock signal, without using a conventional strobe signal for all of the peripheral devices. Using the self-generated strobe signal synchronized to the clock signal, a delay time of the conventional strobe signal due to a high fan-out capability requirement and a long path length may be reduced and an operating frequency of an entire system may be improved.

Apparatus, system and method for generating self-generated strobe signal for peripheral device

A dual layer bus architecture for a system-on-a-chip (SOC) is disclosed. The bus architecture comprises a main bus adapted to connect a microprocessor, an image capture module, and a dual master module to a high density memory and a secondary memory operating independently of the main bus and adapted to connect the dual master module to a high-speed secondary memory.

Dual layer bus architecture for system-on-a-chip

An image processing apparatus for converting image data between a raster format and a block format including an image data processor for providing the image data including a luminance component and at least one chrominance component in the raster format, at least two FIFO memories for storing corresponding image data components, a multiplexer for multiplexing the image data components from the at least two FIFO memories, a line buffer memory for storing outputs of the multiplexer linearly, and an image compressor for receiving the image data components in block format in sequence from the unified line buffer memory and compressing the received image data components. The image processing apparatus may also include an address generator for generating a common read/write address for the line buffer memory.

Image processing apparatus and method for conversion between raster and block formats

A system and method perform video data compression in a manner that limits the need for external memory access. Accordingly, the operational frequency of the local data bus is reduced and power consumption is therefore minimized. In this manner, the present invention is especially amenable to use in mobile systems.

Growing community of inventors

Cheonan-si, South Korea

Hyun-sang Park