Lg Semicon Co., Ltd.

Goldstar Electron Co., Ltd.

Other

Dongwha Pharm. Ind. Co., Ltd.

Lg Electronics Inc.

Hyun S Hwang

Sung June Yoon

Dong Rack Choi

Yong Ho Chung

Dug Keun Lee

Hae Ran Yun

Hee Soon Lee

Sang Hun Jung

Jung A Lee

Chung Ha Choi

Moon Sun Lee

Eun Yi Moon

Jae Gyung Ahn

The present invention relates to a pulsation reducer which includes: an entrance-expanded fuel rail () configured such that a section-expanded fuel rail entrance () expanded to the size of the section of a high-pressure fuel line () is foiled thereon; a spring housing () configured such that a fuel storage space () and a low-pressure movement space () and high-pressure movement space () connected to the fuel storage space () via chimney holes (and) are formed therein; connection parts (and) configured to connect the spring housingwith the entrance-expanded fuel rail (); a low-pressure reduction part () disposed in the low-pressure movement space (), and configured to absorb mixed pulse waves in a low-pressure region; and a high-pressure reduction part () disposed in the high-pressure movement space (), and configured to absorb mixed pulse waves in a high-pressure region.

Pulsation reducer using double-sided multilayer waveform spring

Disclosed is a connector of a fuel pipe for vehicle, which can be easily mounted on or separated from a connector housing by adjusting a latch. The latch includes guide members oppositely located at a prescribed interval, push members vertically located away from the opposite sides of the guide members, and two pair waved resilient members disposed on the upper and lower portions of the guide members. Each guide member has a curved inner surface, a slant surface on the front portion for guiding an insertion of the pipe, a fixed jaw on the rear portion for retaining a bead formed on the peripheral surface of the pipe, and a guide groove formed in the center portion thereof. The two pair waved resilient members elastically connect the push members and the guide members to provide a powerful elastic force to the two pair waved resilient members, so that the guide members are extended outward when the push members are pressed. The connector housing has a guide rail combined with the guide grooves of the latch, thereby allowing the guide members to move back and forth. When the pipe is mounted in or separated from the connector, the guide members are extended outward in a perfect round shape, so that the pipe is easily mounted or detached and is prevented from a separation since the two pair waved resilient members elastically retain a bead of the pipe after mounting.

Connector of a fuel pipe for vehicle

A thick oxide layer is formed over a drain region of an MOS transistor while a thin oxide layer is provided over the source and channel regions. As a result both improved current driving ability and reduced gate induced drain leakage current are achieved.

Method of manufacturing a MOSFET by forming a single oxide layer doping

A method of fabricating a semiconductor device includes the steps of preparing a semiconductor substrate having a first region and a second region, forming a first gate electrode and a second gate electrode over the semiconductor substrate at the first and second regions, respectively, implanting a first impurity ion into the substrate of the first region using the first gate electrode as a mask, implanting a second impurity ion into the substrate of the second region using the second gate electrode as a mask, forming sidewall spacers at both sides of each of the first and second gate electrodes, and implanting the second impurity ion into the first and second regions using the first and second gate electrodes and the sidewall spacers as masks.

Method of fabricating a semiconductor device

The present invention relates to a novel arylsulfonylimidazolone derivative represented by the following formula (I) which shows a superior antineoplastic activity in contrast to the known sulfonylurea antitumor agents as well as little side effect: ##STR1## and its pharmaceutically acceptable salt and stereoisomer, in which - -, R.sub.1, and R.sub.2 are as defined in the specification.

Arylsulfonylimidazolone derivatives as an antitumor agent

The present invention relates to a novel arylsulfonylimidazolone derivative represented by the following formula (I) which shows a superior antineoplastic activity in contrast to the known sulfonylurea antitumor agents as well as little side effect: ##STR1## and its pharmaceutically acceptable salt and stereoisomer, in which ----, R.sub.1, and R.sub.2 are as defined in the specification.

A nonvolatile memory device includes a semiconductor substrate of a first conductivity type; a gate insulating film formed on the substrate; a floating gate having a first region and a second region, the first region lying flat over the gate insulating film and the second region being extended from a first end portion of the first region and perpendicular to the first region; a control gate extending parallel to the second region of the floating gate, lying over the second end portion of the first region of the floating gate and perpendicular to the first region; an inter-insulating layer disposed between the floating gate and the control gate; a first spacer formed at a side wall of the second region of the floating gate and a second spacer formed at a side wall defined by the floating gate and the control gate; a high density source region of a second conductivity type formed in the substrate, being disposed a thickness of the first spacer distant from the floating gate; a first high density drain region of the second conductivity type formed in the substrate, underlapping the floating gate; and a second high density drain region of the second conductivity type formed in the substrate, being disposed a thickness of the second spacer distant from the floating gate and adjacent to the first high density drain region.

Nonvolatile memory device

MOS transistor and method of manufacturing thereof

A method of fabricating a memory device for improving the reliability of the cell area and the driving capability of the peripheral area is disclosed, wherein the method comprises the steps of forming a cell area and a peripheral area by forming a field oxidation layer over a first conductive semiconductor substrate, forming gate oxidation layers of the different thickness from each other over a surface of the substrate which corresponds to the cell area and the peripheral area through once oxidation process, forming a gate over the gate oxidation layer, and implanting a second conductive impurity ion into the substrate partly covered with the gates as a mask to form highly-doped source/drain areas in the respective cell and peripheral area, thereby forming respective MOS transistors on each of the cell area and the peripheral area.

Method of fabricating memory device using a halogen implant

A method of fabricating a nonvolatile memory device including the steps of depositing a first oxide film by chemical vapor deposition over a semiconductor substrate of a first conductivity type; applying a photo etching process to the first oxide film so as to expose a portion of the semiconductor substrate; forming a gate oxide film on the exposed portion of the semiconductor substrate; coating in sequence a first polysilicon film, an insulating film, and a second polysilicon film entirely over the resultant structure; applying an etchback process to the first polysilicon film, the insulating film, and the second polysilicon film so as to form an EEPROM structure, which includes a floating gate at a sidewall of the first oxide film, the insulating film being used as an interlayer insulating film, and a control gate, the floating gate having two regions integrally formed with one region lying flat over the gate oxide film in a first direction and the other region extending from an end portion of the first region and perpendicular to the first region in the first direction, the interlayer insulating film being disposed between the floating gate and the control gate and providing a capacitance; implanting dopants of a second conductivity type into the substrate to form a drain having a shallow junction; removing the first oxide film; coating a second oxide film over the resultant structure; applying an anisotropic etching process to the oxide film so as to form spacers at both sidewalls of the EEPROM structure; and implanting dopants of a second conductivity type into the substrate so as to form a source and a drain having a deep junction. The nonvolatile memory device formed by the process has improved coupling ratio, programming speed, and degree of integration.

Method for fabricating a non-volatile memory device

A method of fabricating a nonvolatile semiconductor memory device so as to improve interface properties between a tunneling oxide layer and a floating gate of the nonvolatile semiconductor memory device is disclosed, wherein the method comprises the steps of forming a tunneling oxide layer on a substrate, forming a floating gate consisting of a plurality of thin silicon layers which are formed through the repeated cyclical process under the low temperature of around 550 degrees C., forming an interposed insulating layer over a whole surface of the floating gate by a selective etching process of the silicon layers; and forming a control gate over a whole surface of the interposed insulating layer.

Method of fabricating nonvolatile semiconductor memory device

A process for the fabrication of an MOS transistor. The process comprises the steps of forming a gate oxide film on a substrate, forming a p.sup.+ polysilicon film doped with p type impurity ions over said gate oxide film, coating an insulating film and a photoresist film over said p.sup.+ polysilicon film, in sequence, subjecting the resultant structure to a patterning to expose a portion of said insulating film, applying an etching method to said exposed insulating film with said photoresist film used as a mask, implanting fluorine ions in said p.sup.+ polysilicon film with resultant insulating film used as a mask, removing the remaining photoresist film, carrying out an annealing method to form a low density p.sup.- source/drain regions, applying an etching method to said p.sup.+ polysilicon film to form a gate with said resultant insulating film used as a mask, removing said resultant insulating film, depositing an oxide film entirely over the resultant structure, applying an anisotropic etching to said oxide film to form spacers at side walls of said gate, implanting p type impurity ions in said substrate at a high density to form high density p.sup.+ source/drain regions neighboring said low density p.sup.- source/drain regions, thereby the device having a storage capacity of not less than 256M can be fabricated more reliably and more advantageously.

Process for fabricating MOS transistor

A method for fabricating an asymmetry HS-GOLD MOSFET by use of a photo etch process in place of a large tilt implantation process, capable of improving a packing density and reducing a junction capacitance of a source region, thereby improving a characteristic of a device to be finally produced. The method includes the steps of forming a gate insulating film and a gate on a p.sup.- type semiconductor substrate, implanting n type impurity ions in the semiconductor substrate so as to symmetrically form n.sup.- type source and drain regions in the semiconductor substrate, forming an insulating film over the entire exposed surface of the resulting structure, subjecting the insulating to an anisotropic etching to form spacers at respective side walls of the gate, implanting n type impurity ions in the semiconductor substrate so as to form n.sup.+ type high concentration source and drain regions respectively adjacent to the n.sup.- type source and drain regions, coating a photoresist film over the entire exposed surface of the resulting structure, subjecting the photoresist film to a patterning to expose one of the spacers disposed toward the source region, removing the exposed spacer, and implanting p type impurity ions in the semiconductor substrate through an area defined by removal of the spacer so as to form a p type halo region.

Growing community of inventors

Seoul, South Korea

Hyun S Hwang