Samsung Electro-mechanics Co., Ltd.

Hyun Paek

Byeong Hak Jo

Jeong Hoon Kim

Yoo Sam Na

Moon Suk Jeong

Jong Ok Ha

Young Wong Jang

Shin Hwan Hwang

Joo Yul Ko

Sol Kim

Hyeon Seok Hwang

Jong Mo Lim

Shinichi Iizuka

Yoo Hwan Kim

Youngsik Hur

Gyu Sub Kim

Nam Heung Kim

Gyu Suck Kim

Wonsun Hwang

Yoosam Na

Su Kyong Kim

Su Gyeong Kim

Su Syeong Kim

A capacitor circuit includes a first capacitor bank and a second capacitor bank. The first capacitor bank includes p switch-capacitor circuits connected to each other in parallel, where p is a natural number of 2 or more, wherein at least two switch-capacitor circuits among the p switch-capacitor circuits have mutually different capacitance values based on a first weight. The second capacitor bank includes q switch-capacitor circuits connected to each other in parallel, where q is a natural number greater than p, wherein at least two of the q switch-capacitor circuits have mutually different capacitance values based on a second weight different from the first weight.

Capacitor circuit and variable capacitance system including the same

Disclosed herein are a transformer and a method of manufacturing the same. The transformer includes: a primary side winding having a loop shape; a secondary side winding formed on the same plane as that of the primary side winding in a remaining section except for at least a section at which it intersects with the primary side winding and having the same loop shape as that of the primary side winding so as to be electromagnetically coupled to the primary side winding; and an intersecting section formed so that the primary side and secondary side windings having the sum of the turn numbers of 3 or more intersect with each other in a two-layer structure, wherein the intersecting section includes at least one point of intermediate node having one side connected in a first layer and the other side connected in a second layer.

Transformer and method of manufacturing the same

A radio frequency switching device includes: a first series switching circuit connected between a first terminal and a second terminal; a first shunt switching circuit connected between one end of the first series switching circuit and a ground; a voltage generation circuit configured to generate a first gate voltage to be output to the first series switching circuit, to generate a second gate voltage to be output to the first shunt switching circuit, and to generate a bias voltage higher than the second gate voltage to control the first shunt switching circuit to enter an off state; a first resistance circuit connected between a signal line between the first terminal and the second terminal, and a bias voltage terminal of the voltage generation circuit; and a second resistance circuit connected between the bias voltage terminal of the voltage generation circuit and a ground terminal of the first shunt switching circuit.

Leakage current reduction type radio frequency switch device

An amplifying apparatus is provided. The amplifying apparatus comprises an amplifying circuit comprising a power amplifier and a bias circuit, the bias circuit is configured to detect an ambient temperature of the power amplifier to output a temperature voltage and regulate an internal current based on an input control signal to supply a bias current obtained by the regulation to the power amplifier; and a temperature control circuit that generates the control signal based on the temperature voltage during initial driving from a transmission mode starting point in time to an input point in time at which an input signal is input and outputting the control signal to the amplifying circuit.

Amplifying apparatus with improved linearity

A radio-frequency switch includes a first series switch including a plurality of series field-effect transistors (FETs) connected in series between a first terminal and a second terminal, a first shunt switch including a plurality of shunt FETs connected in series between the first terminal and a first ground terminal, and a first shunt gate resistor circuit including a plurality of gate resistors respectively connected to gates of the plurality of shunt FETs of the first shunt switch. Respective resistance values of the plurality of gate resistors of the first shunt gate resistor circuit successively increase in a direction away from the first ground terminal toward the first terminal.

Radio-frequency switch with voltage equalization

A radio frequency switch includes a control buffer circuit to generate a first gate voltage and a first body voltage; and a switching circuit to switch at least one signal path in response to the first gate voltage and the first body voltage. The control buffer circuit includes an off voltage detection circuit to detect whether the off voltage is a negative voltage or a ground voltage and output a voltage detection signal, a first gate buffer circuit to output a first gate voltage having a voltage level based on the voltage detection signal and the band selection signal, and a first body buffer circuit to output a first body voltage having a voltage level based on the voltage detection signal, the band selection signal, and the mode signal.

Control buffer circuit and radio frequency switch device

A negative voltage generation circuit includes a clock generation circuit configured to generate a first clock signal, a first voltage control circuit configured to vary a first resistance value based on a magnitude of a power supply voltage and further configured to control a magnitude of a voltage in a first charge node, based on the varied first resistance value, and a first charge pump circuit configured to charge a voltage, controlled by the first voltage control circuit, in a charge mode, based on the first clock signal, and further configured to output a first voltage, generated by the charging, as a first negative voltage.

Negative voltage generation circuit without low-dropout regulator

A negative voltage circuit includes a first charge pump circuit and a second charge pump circuit. The first charge pump circuit is configured to operate in a start-up mode and perform a first charge pumping operation based on a first current to generate a negative voltage. The second charge pump circuit is configured to operate in a normal operating mode subsequent to the start-up mode and perform a second charge pumping operation based on a second current to generate a negative voltage, The first current is higher than the second current, and a speed of the first charge pumping operation is higher than a speed of the second charge pumping operation.

Negative voltage circuit based on charge pump

A radio frequency switching circuit includes a switching circuit comprising a plurality of switching transistors connected between a first terminal and a second terminal, a gate resistor circuit comprising a plurality of gate resistors, each of the plurality of gate resistors having a first node connected to a respective gate of each of the plurality of switching transistors, and a gate buffer circuit comprising a plurality of gate buffers, each of the plurality of gate buffers being connected to a respective second node of each of the plurality of gate resistors, wherein each of the plurality the gate buffers is configured to provide a first gate signal to the gate of each of the plurality of switching transistors through each of the plurality of gate resistors.

Radio frequency switching circuit and apparatus with reduced switching response delay

A negative voltage circuit comprises an inverter circuit that performs a charging operation and a discharging operation, a first dual current circuit supplying a first current for a charging operation of the inverter circuit based on a start-up mode, and a second current for the charging operation of the inverter circuit based on a normal operating mode, a second dual current circuit supplying a third current for a discharging operation of the inverter circuit based on the start-up mode, and a fourth current for the discharging operation of the inverter circuit based on the normal operating mode, a load switching circuit that connects an output node of the inverter circuit to one of an output terminal of a negative voltage circuit and the second operating voltage terminal, and a load capacitor circuit connected between the output terminal and a ground to stabilize a negative voltage at the output terminal.

Negative voltage circuit

A negative voltage circuit includes a dual charging circuit, a pumping capacitor circuit, a dual discharging circuit, an output switch circuit, and a load capacitor circuit. The dual charging circuit is configured to operate in a start-up or normal operating mode during a charging mode, and supply a first current in the start-up mode higher than a second current in the normal operating mode. The pumping capacitor circuit is configured to charge based on a charging current from the dual charging circuit. The dual discharging circuit is configured to operate in the start-up mode or the normal operating mode during a discharging mode, and discharge the pumping capacitor to allow a third current in the start-up mode to flow between the pumping capacitor and the terminal of the second operating voltage. The third current in the start-up mode is higher than a fourth current in the normal operating mode.

Negative voltage circuit based on dual charge pump

A radio frequency switching device includes a switching circuit including first and second transistors; a gate resistor circuit including a first gate resistor and a second gate resistor, the first gate resistor connected to a gate of the first transistor and the second gate resistor connected to a gate of the second transistor; a gate buffer circuit including a first gate buffer and a second gate buffer, the first gate buffer being connected to the first gate resistor to provide a first gate signal to the first transistor through the first gate resistor, the second gate buffer being connected to the second gate resistor to provide a second gate signal to the second transistor through the second gate resistor; and a delay circuit to generate the first gate signal having a first switching time and the second gate signal having a second switching time different than the first switching time.

Radio frequency switching device for fast switching operation

An apparatus for determining an optimum stacking number of an RF switch, in which a gate-off voltage and a body-off voltage are used to control transistors stacked in series to enter an OFF state. The apparatus includes a memory configured to store a peak voltage of a high-frequency signal in a corresponding band, and a gate limiting voltage, a drain-source limiting voltage, and a body limiting voltage in a corresponding process for each of the transistors, and a processor configured to calculate a gate terminal voltage, a drain-source voltage, and a body terminal voltage using the peak voltage, the gate limiting voltage, the drain-source limiting voltage, and the body limiting voltage and to determine an optimum stacking number based on the gate terminal voltage, the gate limiting voltage, the drain-source voltage, the drain-source limiting voltage, the body terminal voltage, and the body limiting voltage.

Apparatus and method for determining optimum stack number of RF switch

A power amplifying apparatus includes a power circuit configured to generate operating power, a random pulse generation circuit configured to be supplied with the operating power and to generate a pulse width modulation signal of which a pulse width is randomly changed over time using an input radio frequency (RF) signal, and a charge pump circuit configured to be supplied with the operating power and to randomly perform a switching operation according to the pulse width modulation signal to generate a negative voltage.

Power amplifying apparatus with spurious signal reduction function

A radio frequency (RF) switch apparatus includes a signal input terminal; a signal output terminal; a first transistor including a first input terminal connected to the signal input terminal, a first output terminal connected to the signal output terminal, a first gate terminal, and a first body terminal, wherein one of the first input terminal and the first output terminal is a source terminal and another one of the first input terminal and the first output terminal is a drain terminal; a first capacitor circuit connected between the first input terminal and the first body terminal; and a second capacitor circuit connected between the first body terminal and the first output terminal; wherein a first capacitance of the first capacitor circuit is greater than a second capacitance of the second capacitor circuit.

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Suwon-si, South Korea

Hyun Paek