Samsung Electronics Co., Ltd.

International Business Machines Corporation

Hyun-Min Choi

Shigenobu Maeda

Jihoon Yoon

Ju-Youn Kim

Ji-hoon Yoon

Sungman Lim

Jun-Tai Kim

Sung-kee Han

Je-Don Kim

Beak-Kwon Son

Gang-Youl Kim

Chul-Min Choi

Jae-Mo Yang

Min-Ho Bae

Hyun-Jo Kim

Seung-hwan Lee

Heon-jong Shin

Juyoun Kim

Yang-Su Kim

Jeong-Hoon Ahn

Hagju Cho

Sang-Woo Pae

Mu-kyeng Jung

Nam-Il Lee

Sangwoo Pae

In-Gyu Park

Jung-Hak Song

Jung-Yeol An

Shincheol Min

Nam-Woog Lee

Keun-Won Jang

Oluwafemi O Ogunsola

Han-Ho Ko

Sung-rey Wi

Sung-Man Lim

Quan WangXiao

Min-jung Jin

A semiconductor device is disclosed. The semiconductor device including writing and reading gate electrodes respectively on first and second active regions on a substrate, a first gate insulation pattern between the first active region and the writing gate electrode, a second gate insulation pattern between the second active region and the reading gate electrode, first and second source/drain junction regions in the first and second active regions at sides of the writing and reading gate electrodes, and a connection structure that connects the first and second source/drain junction regions. The first active region has the same conductivity type as the source/drain junction regions. The second active region has a different conductivity type from the source/drain junction regions.

Anti-fuse one-time programmable (OTP) device

A memory device including one-time programmable memory cells has a semiconductor substrate with a write region and a read region, a write gate provided on the write region, a read gate provided on the read region, first and second junction patterns provided at both sides of the read gate, and insulating dielectric patterns interposed between the write and read gates and the semiconductor substrate. The read region may have a different conductivity type from the first and second junction patterns, and the write region may have the same conductivity type as the first and second junction patterns.

Memory devices including one-time programmable memory cells

An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion. A first distance between the first portion and the second portion may be greater than a width of the second portion in a second direction perpendicular to the first direction.

Semiconductor device including fuse structure

In a semiconductor device and a method of manufacturing the same a fuse structure may be formed during formation of first to third contact plugs connected to a transistor. The fuse structure may include first and second fuse contact plugs having the same height as the first and second contact plugs, and a connection pattern having the same height as the third contact plug. The connection pattern may be connected between the first and second fuse contact plugs.

Semiconductor device and method of manufacturing the same

A one time programmable (OTP) memory device, a method of manufacturing the same, and an electronic device including the same, which lower a programming voltage to enhance programming efficiency, increase reliability of peripheral input/output (I/O) elements used for a design of the OTP memory device, and simplify the design, are provided. The OTP memory device includes a transistor including one of a first gate structure including a high-k dielectric layer, a rare earth element (RE) supply layer, and a second metal layer, a second gate structure including the high-k dielectric layer, a first metal layer, and the second metal layer, and a third gate structure including the high-k dielectric layer and the second metal layer.

One time programmable memory device, method of manufacturing the same, and electronic device including the same

A method, device, a non-transitory computer-readable recording medium for controlling a voice signal by an electronic device including a first microphone, a second microphone, a communication interface, and a processor are provided. The method includes acquiring a first voice signal by using the first microphone; acquiring a second voice signal by using the second microphone; confirming a telephone call mode for performing, by the electronic device, a telephone call with an external electronic device; adjusting a first output attribute corresponding to the first voice signal or a second output attribute corresponding to the second voice signal, based on the telephone call mode; and transmitting the adjusted first voice signal or the adjusted second voice signal to the external electronic device by using the communication interface.

Electronic device and method for controlling voice signal

An electronic device is provided. The electronic includes a camera module and a processor configured to capture at least one image of an object using the camera module, obtain a sound using a microphone operably connected to the processor when the at least one image is captured, determine whether the sound is related to the object, when the sound is determined to be unrelated to the object, change at least one attribute of the sound and store the changed at least one attribute of the sound.

Method for processing sound by electronic device and electronic device thereof

Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level.

E-fuse structure of semiconductor device

The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

A memory device includes first through fourth active regions arranged sequentially along a first direction, and which extend along a second direction different from the first direction; a first gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, and extending along the first direction; a second gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, extending along the second direction, and arranged so that no other gate electrodes are between the first gate electrode and the second gate electrode in the second direction; the first gate electrode extending between a first end and a second end; a first wiring line which is formed on the first gate electrode; a first strap contact, which connects the first wiring line and the first gate electrode between the first active region and the second active region; and a second strap contact, which connects the first wiring line and the first gate electrode between the third active region and the fourth active region.

Memory device

A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.

Fuse structure and method of blowing the same

A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.

Semiconductor device having fin-type active patterns and gate nodes

Growing community of inventors

Uiwang-si, South Korea

Hyun-Min Choi