Electronics and Telecommunications Research Institute

Korea Minting, Security Printing Id Card Operating Corp

Korea Mining, Security Printing & Id Card Operating Corp.

Hyun Mi Kim

Young-Su Kwon

Chun-Gi Lyuh

Chan Soo Kim

Jeongmin Yang

Yong Cheol Peter Cho

Jaehoon Chung

Jin Ho Ryu

Hyeong Seok Jang

Won Gyu Lim

Jong Won Yu

Nak Woong Eum

Jin Ho Han

Kyung Jin Byun

Won Gyun Choe

Seunghyun Cho

Won Seok Jeong

Jin Ki Hong

Jong Hoon Chae

Ho Geun Song

Dong Hoon Shin

Ho Sang Lee

A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.

Reorganizable data processing array for neural network computing

Disclosed is a parallel processor. The parallel processor includes a processing element array including a plurality of processing elements arranged in rows and columns, a row memory group including row memories corresponding to rows of the processing elements, a column memory group including column memories corresponding to columns of the processing elements, and a controller to generate a first address and a second address, to send the first address to the row memory group, and to send the second address to the column memory group. The controller supports convolution operations having mutually different forms, by changing a scheme of generating the first address.

Parallel processor, address generator of parallel processor, and electronic device including parallel processor

Provided is a neural network accelerator which performs a calculation of a neural network provided with layers, the neural network accelerator including a kernel memory configured to store kernel data related to a filter, a feature map memory configured to store feature map data which are outputs of the layers, and a Processing Element (PE) array including PEs arranged along first and second directions, wherein each of the PEs performs a calculation using the feature map data transmitted in the first direction from the feature map memory and the kernel data transmitted in the second direction from the kernel memory, and transmits a calculation result to the feature map memory in a third direction opposite to the first direction.

Neural network accelerator including bidirectional processing element array

Provided is a method for a plurality of processing elements to filter a plurality of pixel blocks in a plurality of picture partitions for a single frame image. The method for filtering pixel blocks includes: checking the status of a second boundary pixel block adjacent to a picture partition boundary, the second boundary pixel block being one of a plurality of pixel blocks in a second picture partition and neighboring a first boundary pixel block in a first picture partition, the first boundary pixel block neighboring the picture partition boundary; selecting a filtering area for the first boundary pixel block based on the status of the second boundary pixel block; and filtering the filtering area for the first boundary pixel block.

Method and apparatus for filtering pixel blocks

Provided is a combi-card, i.e. a combination type IC card, which can be used in either contact and non-contact manner, and a communication system using the same, and the combi-card is provided with a transponder chip module formed with a RF antenna and attached in a recess region of a card body and is characterized by the use of the RF antenna of the transponder chip alone as a transmitting and receiving antenna.

Combi card and communication system using thereof

An electromagnetic bandgap (EBG) pattern structure includes a nonconductive substrate and a pattern assembly formed on the substrate. The EBG pattern structure also includes regularly arranged closed-loop patterns and open-loop patterns, both of which are made of a conductive material. The EBG pattern structure can be used to manufacture new security products by applying its frequency characteristics to securities or IDs and variously used in security technologies for preventing forgery and alteration because various security codes can be created by adjusting the variables of its EBG pattern.

Electromagnetic bandgap pattern structure, method of manufacturing the same, and security product using the same

In an apparatus for recognizing a security code having an electromagnetic band gap (EBG) pattern which uses reflection and transmission characteristics of the EBG pattern, a voltage controlled oscillator generates a signal to a power divider, which divides the power of the signal into halves, and outputs a first signal through a waveguide to be incident on the EBG pattern. The waveguide receives a signal reflected from the EBG pattern and outputs the reflected signal to a phase detector. A circulator outputs the second signal to the phase detector, which detects the phase difference between the reflected signal and the second signal, and outputs phase difference data to a data control unit, which determines whether the security code having the EBG pattern is recognized using the phase difference data. In an alternate embodiment, the voltage control oscillator is controlled to sequentially generate signals using power difference data.

Apparatus for recognizing security code having electromagnetic band-gap pattern

Growing community of inventors

Daejeon, South Korea

Hyun Mi Kim