Electronics and Telecommunications Research Institute

Hyun-Kyu Yu

Cheon-Soo Kim

Mun-Yang Park

Min Sang Park

Seon-Ho Han

Kee-Soo Nam

Sang-Jin Byun

Hyoung-Seok Oh

Sang-Won Kang

Nam Hwang

Dae-Yong Kim

Young-Jae Lee

Jung-Woo Park

Yong-Sik Youn

Won-Gu Kang

Jang-Hong Choi

Jae-Hong Jang

Chung-Hwan Kim

Provided is a wireless transceiving apparatus for variability of signal processing band, in which at least one resonator of an analog processor and a VCO are simultaneously controlled using a frequency synthesizer, and a frequency of the VCO and a resonance frequency of the analog processor are controlled to have a rational number ratio, thereby capable of varying the signal processing band. The wireless transceiving apparatus includes: an analog processor having a plurality of resonators on a path of transmission/reception signals, for performing analog signal processing; a digital processor for performing digital signal processing on an output signal of the analog processor or data to be transmitted to the analog processor; and a frequency synthesizer for providing a local oscillation (LO) frequency and a controlling signal to the resonators of the analog processor so as to vary a signal processing band of the analog processor.

Wireless transceiving apparatus for variability of signal processing band

A clock and data recovery apparatus reduces current consumption and enables easy integration. The inventive apparatus includes a first loop including a frequency/phase detection unit, a first charge pump unit, a multiplexing unit, a filtering unit, and a voltage controlled oscillator unit operating at a speed &#xbc; as fast as that of received data; a second loop having a phase detection unit operating at a speed &#xbc; as fast as a speed of received data, a second charge pump unit suitable for the phase detection unit, the multiplexing unit, the filtering unit, and the voltage controlled oscillator unit; a frequency lock detection unit for judging whether a frequency of a feedback clock signal falls within a desired frequency range; and a data recovery unit for recovering data from received data.

Clock and data recovery apparatus

Provided is a frequency lock detector which includes one counter and a clock number difference detector for detecting a clock number difference while not increasing complexity according to the counting number N to compare the frequencies of two clock signals whose phases are not synchronous to each other and determine whether the difference between the frequencies of the two signals is within a desired frequency accuracy. The frequency lock detector includes: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector.

Frequency lock detector

The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

Structure of delta-sigma fractional type divider

There is provided a transformer for varying an inductance value, which adjusts a tuning range of the inductance without decrease of the inductor's capability by selectively connecting switches to inductors and controls an amount of magnetic flux. And the transformer consists of multiple inductors formed on a semiconductor substrate, which including N number of metal lines, N number of ports made by twisting the metal lines in the form of a symmetric circuit, wherein a certain number of ports among the N number of ports, which are connected to switch elements.

Transformer for varying inductance value

Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique

Provided is a low noise amplifier with a common source and a source degeneration, which has linearity, power gain, noise factor, and lossless input matching. The low noise amplifier includes: a first inductor having one terminal connected to an input terminal receiving a signal; a second inductor having one terminal connected to a ground; a MOS transistor having a gate connected to the first inductor, a source connected to the other terminal of the second inductor, and a drain transmitting a signal; and a variable capacitor connected between the source and gate of the MOS transistor and varying an input matching frequency at the input terminal.

Low noise amplifier for wideband tunable matching

An amplifier including an amplifier transistor that operates in an active region has main current flowing therethrough according to input voltage, and a linear transistor that is driven by offset positive-polarity input voltage to operate in a linear region and has auxiliary current flowing therethrough. The main current and auxiliary current are added to become output current. The offset positive-polarity voltage corresponds to the sum of AC component of the input voltage and an offset DC voltage. Here, a transistor stacked on the linear transistor is coupled to the amplifier transistor to secure the linear region operation of the linear transistor. The stacked transistor is driven by a voltage having polarity opposite to that of the input voltage.

Amplifier and method for canceling nonlinearity in amplifier

A method of forming an HF power device. The method includes forming a semiconductor layer as a first conductive type on a semiconductor substrate; etching the semiconductor layer forming a first trench; doping an impurity in the neighborhood of the first trench forming a first impurity layer; burying a conduction film into the first trench; etching the semiconductor layer forming a second trench; forming a field oxide film buried into the second trench; forming a gate electrode on a surface of the semiconductor layer; forming a source on the surface of the semiconductor layer; forming a drain area on the surface of the semiconductor layer; forming an LLD area on the surface of the semiconductor layer between the drain area and the gate electrode; forming a first metal electrode; and forming a second metal electrode electrically connected to the LDD area.

Method of making a HF LDMOS structure with a trench type sinker

A method for fabricating an inductor device includes the steps of forming a plurality of trenches in a substrate by selectively etching the substrate, implanting dopants into sidewalls and bottom portion of each trench, forming an oxide layer by oxidizing the trenches and the substrate and simultaneously forming a doped layer in the surroundings of the trenches by diffusing the dopants into the substrate, and forming a dielectric layer on a resultant structure to fill the entrance of the trenches, thereby forming air-gap layers inside the trenches, thereby reducing a parasitic capacitance and a magnetic coupling.

Integrated inductor device and method for fabricating the same

Inductors used for impedance matching in the radio frequency integrated circuits is disclosed. In the integrated inductor device according to the present invention, an additional electrode is arranged in surroundings of an inductor metal line, and the reverse bias voltage is applied to the region between the substrate and the electrode so as to form a depletion layer. Therefore, the substrate biasing is effected and thus an inductor having improved performance can be formed by decreasing the parasitic capacitance between the inductor metal line and the substrate. The present invention can also be applied to another semiconductor device having metal lines and pads.

Inductor devices using substrate biasing technique

An inductor device with a MOS transistor internally installed is disclosed, in which an inductor can be arbitrarily connected in series or in parallel to the respective terminals of MOS transistors by applying a multi-layer wiring technique, thereby reducing the chip area. Within an inductor structure, MOS transistors which have an active region width of W .mu.m are formed in the number of n, and an inductor wire is connected to an arbitrary terminal of the MOS transistors by employing a multi-layer metal wiring process. Thus the inductor is connected to an arbitrary terminal of the MOS transistors in series. Thus an inductor device in which MOS transistors having a channel width of W.times.n .mu.m are internally installed is formed.

MOS transistor embedded inductor device using multi-layer metallization

Methods for foming an inductor devices used for impedance matching in the radio frequency integrated circuits are disclosed. In the integrated inductor device according to the present invention, an additional electrode is arranged in surroundings of an inductor metal line, and the reverse bias voltage is applied to the region between the substrate and the electrode so as to form a depletion layer. Therefore, the substrate biasing is effected and thus an inductor having improved performance can be formed by decreasing the parasitic capacitance between the inductor metal line and the substrate. The present invention can also be applied to another semiconductor device having metal lines and pads.

Method for forming an inductor devices using substrate biasing technique

There are disclosed a semiconductor device having electrical elements buried a SOI substrate and a manufacturing method thereof, the manufacturing method of the invention comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon layer thus doped to form a mirror surface; (e) depositing an insulating layer for connection on the handling wafer, and performing a thermal process to bond the handling wafer and the mirror surface through the insulating layer for connection; and (f) polishing the seed wafer until the first isolating insulator layer as a polishing stopper is exposed, to form the SOI substrate having an active region where a device is formed, by the invention the efficiency of chip area can be promoted.

Growing community of inventors

Daejon, South Korea

Hyun-Kyu Yu