Xilinx, Inc.

Hyun Kwon

Ygal Arbel

James J Murray

Mrinal J Sarmah

Nishit Patel

Maurice Penners

Tejus Siddagangaiah

Ronan Keryell

Cyril Chemparathy

Andrew Gozillon

Examples herein describe compiling source code for a heterogeneous computing system that contains jump logic for executing multiple accelerator functions. The jump logic instructs the accelerator to execute different functions without the overhead of reconfiguring the accelerator by, e.g., providing a new configuration bitstream to the accelerator. At start up when a host program is first executed, the host configures the accelerator to perform the different functions. The methods or system calls in the host program corresponding to the different functions then use jump logic to pass function selection values to an accelerator program in the accelerator that inform the accelerator program which function it is being instructed to perform. This jump logic can be generated by an accelerator compiler and then inserted into the host program as a host compiler generates the executable (e.g., the compiled binary) for the host program.

Performing multiple functions in single accelerator program without reload overhead in heterogenous computing system

Systems and method for synchronizing access to buffered data are disclosed. In such a method, video data is buffered in a frame buffer memory by a producer device. A write level indicator is provided to a synchronizer by the producer device. A read level indicator is provided to the synchronizer by a consumer device. The synchronizer compares the write level indicator with the read level indicator to determine a difference. The consumer device is informed by the synchronizer when the difference meets a sub-frame threshold. The consumer device reads the buffered data from the frame buffer memory on a sub-frame-by-sub-frame basis responsive to the informing.

Synchronizing access to buffered data in a shared buffer

A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Circuits for and methods of enabling the access to data

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San Jose, CA, United States of America

Hyun Kwon