Key Foundry Co., Ltd

Magnachip Semiconductor, Inc.

Sk Keyfoundry Inc.

Hyun Kwang Shin

Jung Hwan Lee

Tae Hoon Lee

Yon Sup Pang

Kyung Ho Lee

A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.

Semiconductor device with controllable channel length and manufacturing method thereof

A trench power MOSFET includes a body region disposed on a semiconductor substrate, a trench passing through the body region, an top electrode and a bottom electrode spaced apart from each other in a vertical direction in the trench, an inter-electrode dielectric layer disposed between the top electrode and the bottom electrode, and a plurality of dielectric layers, disposed between a sidewall of the trench and the bottom electrode, comprising a first oxide layer disposed on the sidewall of the trench, an barrier layer disposed on the first oxide layer, and a second oxide layer disposed on the barrier layer. The barrier layer is formed of a material different from materials of the first and second oxide layers.

Structure and method for manufacturing a trench power MOSFET

A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.

Semiconductor device with controllable channel length and manufacturing method of semiconductor device with controllable channel length

A semiconductor device includes a substrate, a buried doped layer formed on the substrate, a trench gate formed on the buried doped layer, a source region formed adjacent the trench gate, an interlayer dielectric layer formed on the trench gate and the source region, a source contact plug formed to extend and connect to the source region, and a drain contact plug, extending and connecting to the buried doped layer, formed deeper than the source contact plug.

Semiconductor device having vertical DMOS and manufacturing method thereof

A semiconductor device includes a first N-type deep well region and a second N-type deep well region formed in a substrate, an N-type diffused well region formed between the first N-type deep well region and the second N-type deep well region, wherein a concentration of the N-type diffused well region is less than a concentration of the first N-type deep well region or the second N-type deep well region, a first P-type well region formed in the first N-type deep well region, a second P-type well region formed in the N-type diffused well region, an insulating film formed to be in contact with the first P-type well region, and a silicide formed on the N-type diffused well region, such that a Schottky barrier diode is formed between the silicide and the N-type diffused well.

Semiconductor device comprising Schottky barrier diodes

A method of fabricating a semiconductor device including a diffused metal-oxide-semiconductor (DMOS) transistor, an n-type metal-oxide-semiconductor (NMOS) transistor, and a p-type metal-oxide-semiconductor (PMOS) transistor includes forming separation regions in a semiconductor substrate, forming a gate insulating film, forming a DMOS gate electrode on the gate insulating film, forming a first mask pattern on the semiconductor substrate, performing a first ion implantation process, forming a second mask pattern on the semiconductor substrate, performing a second ion implantation process, forming a third mask pattern on the semiconductor substrate and performing a third ion implantation process into the semiconductor substrate, and forming a fourth mask pattern on the semiconductor substrate and performing a fourth ion implantation process.

Method of fabricating DMOS and CMOS transistors

A semiconductor device and a fabricating method thereof are provided, in which the semiconductor device includes a semiconductor substrate with a trench formed therein, a bottom electrode placed at a lower inner portion of the trench, the bottom electrode having an uneven upper surface, an insulating layer formed on an upper portion of the bottom electrode and on a sidewall of the trench, and a top electrode placed at an upper portion of the bottom electrode inside the trench, the top electrode having a top electrode which is uneven, in which the top electrode is so configured that the top electrode is inclined toward a center portion.

Growing community of inventors

Cheongju-si, South Korea

Hyun Kwang Shin