Samsung Electronics Co., Ltd.

Hyun-Kwan Yu

Dongsuk Shin

Dong-Suk Shin

Min-Hee Choi

Seokhoon Kim

Chanjin Park

Sihyung Lee

Namkyu Cho

Kang Hun Moon

Sanggil Lee

Sahwan Hong

YongKuk Jeong

Kieun Kim

Kooktae Kim

Youngdal Lim

Sunyoung Lee

Sung-Min Kim

Cheol-Woo Park

Dong-won Kim

Han-jin Lim

Seok Hoon Kim

Seung-hun Lee

Hanjin Lim

Ryong Ha

Pan-Kwi Park

Ji Hoon Cha

Hyoung Soo Ko

Ki-eun Kim

Alexander Schmidt

Si Hyung Lee

Dong-Gwan Shin

Moonhan Park

In Kook Jang

Anthony Payet

Kyungyeon Hwang

Woonki Shin

Woon-Ki Shin

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, and a gate dielectric layer between the gate electrode and the semiconductor patterns. An inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. A first thickness of the horizontal portion is less than a second thickness of the vertical portion. The second thickness of the vertical portion is less than a third thickness of the corner portion.

Semiconductor device and method of fabricating the same

A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Semiconductor devices having variously-shaped source/drain patterns

A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

Semiconductor devices with bent portions

Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

Semiconductor device

A simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, imaging generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors (EDF) respectively for the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating first to m-th epitaxy times for first to m-th effective open silicon densities.

Simulation method and system

A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.

Semiconductor device blocking leakage current and method of forming the same

An etching method is disclosed. The etching method comprises providing on a substrate a structure comprising a recess region formed therein. The recess region includes an inner part and a mouth part whose width is less than that of the inner part. The etching method further comprises performing a clean-then-etch process to remove at least a portion of etching object formed outside the recess region. The performing a clean-then-etch process comprises performing a cleaning process to fill at least a portion of the recess region with a cleaning solution, and performing a wet etch process to the substrate in a state that the cleaning solution remains in the recess region.

Etching methods and methods of manufacturing semiconductor devices using the same

A method of manufacturing a semiconductor device includes forming an active fin extending longitudinally in a first direction along a surface of a substrate, forming a field insulating layer on the substrate, the field insulating layer covering a part of the active fin, forming a dummy gate electrode on the field insulating layer and the active fin, the dummy gate electrode extending in a second direction different from the first direction, forming a spacer on the sides of the dummy gate electrode, and removing the dummy gate electrode by a wet etching process that includes rinsing the dummy gate electrode intermittently during an etching away of the dummy gate electrode.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.

Methods of forming semiconductor devices are provided. The methods may include forming a gate pattern on an active region of a substrate. The methods may further include performing a deoxidization treatment on the substrate.

Methods of forming semiconductor devices

A semiconductor device is fabricated by providing a substrate including a silicon channel layer and a silicon-germanium channel layer, forming gate structures disposed on the silicon channel layer and on the silicon-germanium channel layer, forming a first protection layer to cover the resultant structure including the gate structures, and injecting hydrogen and/or its isotopes into the silicon-germanium channel layer. The silicon and silicon-germanium channel layers may be oriented along a &#x3c;100&#x3e; direction. Related devices are also described.

Methods of fabricating semiconductor devices with silicon-germanium channels including hydrogen

Growing community of inventors

Suwon-si, South Korea

Hyun-Kwan Yu