Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Hyun-jung Lee

Seung-hun Lee

Nam-Gun Kim

Jeong-yun Lee

Eun-Ok Lee

Gyuhwan Oh

Sun-ghil Lee

Heesook Park

Jung-han Lee

Myung-il Kang

Kyungho Jang

Sun-wook Kim

Sung-Min Kim

Cheol Kyu Kim

Sang-Bom Kang

Heon-jong Shin

Jong-Ryeol Yoo

Seong-Hoon Jeong

Seok-Hoon Kim

Edward Namkyu Cho

Tae-Ouk Kwon

Chung-Geun Koh

Kyung-Seok Oh

Kwan-Yong Lim

Seung Hun Lee

Dong-Woo Kim

Young-wook Park

Jin-bum Kim

Sung-Hee Cho

Hyun-hwa Oh

Jong-Hwan Park

Min-Hee Choi

Sun Jung Kim

Moon Seung Yang

Seok-hoon Kim

Dong-jae Lee

Young-kuk Kim

Cho-eun Lee

Jeon-Il Lee

Sun-jung Kim

Ui-hui Kwon

Jong-Woon Moon

Se-min Kim

Eun Hye Choi

Jeong-yong Song

Sung-uk Jang

Dong-myoung Kim

Keum-seok Park

A medical image transmitting method includes obtaining a medical image generated by imaging an object; performing a first determination to determine whether the object has an abnormality, based on the medical image; performing a second determination to determine, based on the first determination, whether to transmit at least one assistance image associated with the medical image; and when the object has no abnormalities, transmitting, to an external apparatus, the medical image, thereby minimizing a data processing amount and a data transmission amount.

Medical imaging apparatus to automatically determine presence of an abnormality including a determination to transmit an assistance image and a classified abnormality stage

An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Integrated circuit device and method of manufacturing the same

A semiconductor device includes a first region having a first active pattern with first protrusion portions and first recess portions, and a second region having a second active pattern with second protrusion portions and second recess portions. First gate patterns are on the first protrusion portions. Second gate patterns are on the second protrusion portions. A first source/drain region is on one of the first recess portion of the first active pattern between two of the first gate patterns. The first source/drain region has a first reinforcing epitaxial layer at an upper portion thereof. A second source/drain region is on one of the second recess portions of the second active pattern between two of the second gate patterns. The second source/drain region has a second reinforcing epitaxial layer having an epitaxial growth surface that is shaped differently than a first epitaxial growth surface of the first reinforcing epitaxial layer.

Integrated circuit semiconductor devices including a metal oxide semiconductor (MOS) transistor

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

Semiconductor devices having lower and upper fins and method for fabricating the same

A semiconductor device includes a fin-type active area, nanosheets, a gate, a source/drain region, and insulating spacers. The fin-type active area protrudes from a substrate in a first direction. The nanosheets are spaced from an upper surface of the fin-type active area and include channel regions. The gate is over the fin-type active area. The source/drain region is connected to the nanosheets. The insulating spacers are in the fin-type active area and between the nanosheets. Air spaces are between the insulating spacers and the source/drain region based on positions of the insulating spacers.

Semiconductor device

A semiconductor substrate and a semiconductor device are provided. The semiconductor substrate includes a base substrate, a first silicon germanium layer on the base substrate and a second silicon germanium layer on the first silicon germanium layer. A germanium fraction of the second silicon germanium layer decreases in the direction away from the base substrate, and a germanium fraction of a lowermost part of the second silicon germanium layer is greater than a germanium fraction of an uppermost part of the first silicon germanium layer.

Semiconductor substrate and semiconductor device including the same

Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed.

Methods of manufacturing semiconductor devices

A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.

Semiconductor devices including spacers

Methods of manufacturing semiconductor devices including air gap spacers

Semiconductor devices including air gap spacers

A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

Method for manufacturing semiconductor device

A method of forming a transistor induces stress in the channel region using a stress memorization technique (SMT). Impurities are implanted into a substrate adjacent a gate electrode structure to produce an amorphous region adjacent the channel region. The amorphous region is then recrystallized by forming a metal-oxide layer over the amorphous region, and then thermally treating the same. The crystallization creates compressive stress in the amorphous region. As a result, stress is induced in the channel region of the substrate located under the gate electrode structure.

Methods of forming transistors and CMOS semiconductor devices using an SMT technique

Growing community of inventors

Suwon-si, South Korea

Hyun-jung Lee