Samsung Electronics Co., Ltd.

Hyun-jong Lee

Chul-hong Park

Raheel Azmat

Sang-jun Park

Deepak Sharma

Si-Young Choi

Jung-Ho Do

Rwik Sengupta

Sang-Pil Sim

Kwanyoung Chun

Dong-Woon Park

Yong-Kug Bae

Chulhong Park

Soo-Han Choi

Yusun Lee

Sooyeon Jeon

Roo-Li Choi

Duck-Hyung Hur

Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Integrated circuit and standard cell library

A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.

Semiconductor device and method of forming the same

A design rule generating method is provided. The method includes receiving a test pattern, providing a plurality of workflows, which correspond to the test pattern and are preset in relation to a lithography model and a mask generation method, and performing simulation on the test pattern according to a workflow selected from the workflows.

Rule generating apparatus and method using lithography simulation

A method of forming a pattern includes defining a plurality of patterns, defining a plurality of pitch violating patterns that contact the plurality of patterns and correspond to regions between the patterns, classifying the plurality of pitch violating patterns into a first region and a second region that is adjacent to the first region, selecting one of the first region and the second region, and forming an initial pattern defined as the selected first or second region. The selecting includes performing at least one of i) selecting a region that contact dummy patterns, ii) selecting a region of a same kind as one region, and iii) selecting a region that contacts a concave part of an enclosure from the first region and the second region.

Method of forming a pattern

A method of forming a pattern includes forming a plurality of target patterns, forming a plurality of pitch violating patterns that make contact with the plurality of target patterns and are disposed between the plurality of target patterns, classifying the plurality of pitch violating patterns into a first region and a second region adjacent to the first region, and forming an initial pattern corresponding to one of the first region and the second region.

Method of forming pattern, reticle, and computer readable medium for storing program for forming pattern

Growing community of inventors

Hwaseong-si, South Korea

Hyun-jong Lee