Samsung Electronics Co., Ltd.

Sewon Cellontech Co., Ltd.

Hyun-Jo Kim

Jang-Eun Lee

Se-Chung Oh

Jun-Soo Bae

Soo-Hun Hong

Young-Ki Ha

Hwa-Sung Rhee

Kyung-tae Nam

Hee-Soo Kang

Jong-Mil Youn

Jae-yup Chung

Kyung-Tae Nam

Hee-Don Jeong

Ju-Youn Kim

In-gyu Baek

Sang-Pil Sim

Jun-Ho Jeong

Joong-won Jeon

Hee-Don Jung

In-Gyu Baek

Se-wan Park

Dae-Lim Kang

Jeong-Hee Park

Tae-Wan Kim

Kyu-Mann Lee

Bo-Cheol Jeong

I-Hun Song

Yoon-seok Lee

Seok-Jae Chung

Myeong-Cheol Kim

Cheol Kyu Kim

Sang-Bom Kang

Young-Soo Yoon

Hyun-Min Choi

Jong-Seo Hong

Wook-Je Kim

Jun-ho Jeong

Mu-kyeng Jung

Je-min Yoo

Yang-Soo Son

Jong-shik Yoon

Jeong-Hyo Lee

Ji-Yong Ha

Seong-Yul Park

Jae-Deog Jang

Sae-Bom Lee

Young-Su Chung

Seok-Jung Kim

Ju-Hee Park

Hyun-Shin Park

Ji-Chul Yu

Min-Kwon Choi

Han-Ii Yu

Cheong-Ho Jang

Kyu-man Cha

Se-Ken Yeo

An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.

Electrostatic discharge protection devices

Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Integrated circuit (IC) device

Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

Semiconductor device

A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.

Semiconductor devices having 3D channels, and methods of fabricating semiconductor devices having 3D channels

A semiconductor device includes: a semiconductor substrate including an active region and a gate structure on the active region. The gate structure includes a gate insulating film; a work function adjusting film on the first gate insulating film; a separation film on the work function adjusting film; and an oxygen capturing film on the separation film and configured to capture oxygen introduced from the outside of the first gate structure. The oxygen capturing film is spaced apart from a top surface of the first gate insulating film by about 70 &#x212b; to about 80 &#x212b;.

Semiconductor devices including gate structures with oxygen capturing films

An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalls of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalls of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.

Integrated circuit devices and methods of manufacturing the same

A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.

An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.

Integrated circuit device and method of manufacturing the same

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Seoul, South Korea

Hyun-Jo Kim