Samsung Electronics Co., Ltd.

Hyundai Motor Company

Korea Institute of Science and Technology

Hyun-Jin Shin

Jung-Hwan Kim

Ji-Sung Kim

Ho Young Shin

Gyuseong Kim

Jung Ho Kim

Sang-Hoon Lee

Ji-Hoon Choi

Seulye Kim

Young-Dae Kim

Hong-suk Kim

Bong-hyun Kim

SeungHyun Lim

Hun-hyeong Lim

Man-Sug Kang

Seung-Mok Shin

Dongkyum Kim

Jintae Noh

Jai-Dong Lee

Ji Hyung Park

Won-Seok Yoo

Yong-Sun Lee

Hoyoung Shin

Ki Won Yeom

Yong-Seok Cho

Sanggyeong Won

Han-Vit Yang

Joong-Ho Lee

Hyung Lae Lee

Gyu Seong Kim

Hee Seok Jeong

Myeong Hee Oh

Sang Gyeong Won

Ki Woon Yeom

A flash memory includes a first memory cell connected with a selected word line and a first bit line, a second memory cell connected with the selected word line and a second bit line, a sense amplifier that provides a sensing line with a sensing current for sensing data stored in the first memory cell or the second memory cell, a bit line selection circuit that selects a bit line by connecting the sensing line with the first bit line or the second bit line, and a margin read test circuit that performs a margin read test operation in which the margin read test circuit provides the sensing line with a margin current for testing a read margin of the data stored in the first memory cell or the second memory cell that is connected to the selected bit line.

Flash memory for performing margin read test operation and margin read test system including the same

A non-volatile memory device is provided. The non-volatile memory device may include a memory cell array, a first pumping circuit configured to output a first pumping voltage, a second pumping circuit configured to pump the first pumping voltage of the first pumping circuit to output a second pumping voltage, and a pumping circuit control unit which is connected to the first pumping circuit and the second pumping circuit and configured to output at least one of the first pumping voltage and the second pumping voltage to the memory cell array. The first pumping circuit may be enabled in a first mode and a second mode different from the first mode, and the second pumping circuit may be disabled or not enabled in the first mode and enabled in the second mode.

Nonvolatile memory devices having pumping circuits operable in multiple modes

Provided a voltage generating circuits including assist circuits and operating methods thereof. The voltage generating circuit which includes an assist circuit that generates an assist signal indicating an enable mode or a disable mode. When a first power supply voltage is lower than an assist reference voltage, the assist signal indicates the enable mode, and a compensation circuit generates a compensation signal based on the first power supply voltage. An internal voltage converter generates a regulated voltage based on the first power supply voltage, and a charge pump circuit generates a pump voltage based on the regulated voltage. The compensation signal compensates for the regulated voltage.

Voltage generating circuits including assist circuits and operating methods thereof

A nonvolatile memory device includes a memory cell array including a plurality of memory cells that are programmed based on a high voltage, a high voltage generator to generate the high voltage by boosting an input voltage based on a pumping clock, a pumping clock generator to generate the pumping clock, a high voltage detector to generate a detection signal by comparing an adjustment voltage with a reference voltage, a programming current controller to adjust a programming current flowing through each of selected memory cells of the plurality of memory cells; and a control logic to adjust a frequency of the pumping clock and a current driving capability of the programming current based on the detection signal during a programming period with respect to the selected memory cells. The detection signal includes information indicating whether the high voltage reaches to a target voltage.

Nonvolatile memory device and memory system including thereof

A nonvolatile memory device includes a memory cell array including a main memory area and a dummy memory area, a row decoder, a bit line selection circuit, a data input/output circuit, a control circuit, and a voltage generator. The bit line selection circuit is configured to select a first main bit line during a program time and is configured to select a dummy bit line during a column address switch time. During the column address switch time, a second main bit line is selected. The voltage generator is configured to output, to the row decoder, a source line voltage to be applied to a selected source line during the program time and during the column address switch time, wherein the source line voltage is maintained at a voltage level during the program time and during the column address switch time.

Nonvolatile memory devices and operating methods thereof

A sensing circuit of nonvolatile memory device includes a precharge current generator, an adjusting transistor, and an adaptive control voltage generator. The precharge current generator connected to a sensing node and generates a precharge current provided to a bit-line of the nonvolatile memory device, in response to a precharge signal. The adjusting transistor, connected between the sensing node and a first node, adjusts an amount of the precharge current provided to the bit-line in response to a first control voltage. The adaptive control voltage generator generates a control current proportional to an operating temperature, in response to the precharge signal and a second control voltage and boosts a level of the first control voltage in proportion to the operating temperature. The second control voltage is inversely proportional to the operating temperature.

Sensing circuits and methods of operating nonvolatile memory devices based on operating temperatures

A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.

Semiconductor device and method for fabricating the same

A semiconductor memory device includes a memory cell array including a plurality of memory cells connected to a plurality of bit lines, a control signal generating circuit configured to generate a first control signal in response to a first operating temperature of the semiconductor memory device and a second control signal in response to a second operating temperature of the semiconductor memory device, a precharge circuit configured to provide a precharge current to a first bit line of the plurality of bit lines in response to an enable signal, and a boost circuit configured to provide a boost current to the first bit line in response to the enable signal, wherein the magnitude of the boost circuit is responsive to one of the first and second control signals.

Semiconductor memory device

A memory device includes a memory cell, a bit line connected to the memory cell, a control voltage generator configured to generate a proportional to absolute temperature (PTAT) current and generate an analog control voltage inversely proportional to the PTAT current, and a load current control circuit configured to control a first load current supplied to the bit line based on the analog control voltage.

Memory device and memory system having the same

A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

Method of manufacturing a semiconductor device

A precharge control signal generator and a semiconductor memory device include a precharge control signal generating circuit which generates a precharge control signal and applies the precharge control signal to a sensing circuit, and a sensing circuit configured to precharge a bit line connected to a memory cell according to the precharge control signal and read data stored in the memory cell. The precharge control signal controls the sensing circuit so that a precharge time is adjusted according to operating temperature.

Precharge control signal generator and semiconductor memory device therewith

The disclosure relates to a system for controlling devices and information on a network by hand gestures, and more particularly, to a system for controlling devices and information on a network by hand gestures in which a device or a file to be controlled is selected by a user and a display device is pointed so that information and data can be shared and that various devices can be coupled to each other easily and can be controlled easily. The system for controlling devices and information on a network by hand gestures can remarkably improve the interaction between various input and display devices and a user under a ubiquitous computing environment.

System for controlling devices and information on network by using hand gestures

Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

Methods of manufacturing a semiconductor device

The present invention relates to a method and system for preventing reverse rotation operation of an engine using a system that includes a crank angle sensor (CAS), a cam position sensor (CPS), and an engine control unit for receiving signals from the CAS and the CPS to perform engine control. The method includes determining if a piston in a specific cylinder is at a predetermined location using a level of a CPS signal at a leading edge and a trailing edge of a CAS signal; determining if the engine is rotating in reverse using the CPS signal level at the leading edge and trailing edge of the CAS signal in the case where it is determined that the piston of the specific cylinder is at the predetermined location; and discontinuing operation of the engine if it is determined that the engine is undergoing reverse rotation.

Growing community of inventors

Hwaseong-si, South Korea

Hyun-Jin Shin