Samsung Electronics Co., Ltd.

Seoul National University

Hyun-Jae Song

Jae-Ho Lee

Seong-jun Park

Hyun-jong Chung

Jin-seong Heo

David Seo

Kyung-Eun Byun

Jae-ho Lee

Hee-jun Yang

Hyeon-jin Shin

Jae-hong Lee

Hyung-cheol Shin

In-kyeong Yoo

Yun-sung Woo

Chang-Hyun Kim

Ho-jung Kim

Chang-seung Lee

Yong-sung Kim

Jang-Hee Lee

Joo-ho Lee

Dong Wook Lee

Chang-Seok Lee

Dong-Wook Lee

Hyeon-Jin Shin

Kaoru Yamamoto

Kee-Young Jun

Geun-O Jeong

Sung-Joo An

Min-Hyun Lee

Keun-Wook Shin

Hyun-Jong Chung

Jin-Seong Heo

Yun-Sung Woo

Seong-Jun Park

Hee-Jun Yang

In a plasma deposition method, a substrate is loaded onto a substrate stage within a chamber. A first plasma is generated at a region separated from the substrate by a first distance. A first process gas is supplied to the first plasma region to perform a pre-treatment process on the substrate. A second plasma is generated at a region separated from the substrate by a second distance different from the first distance. A second process gas is supplied to the second plasma region to perform a deposition process on the substrate.

Plasma deposition method, plasma deposition apparatus and method of manufacturing semiconductor device

A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.

Memory device using graphene as charge-trap layer and method of operating the same

A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Graphene device and electronic apparatus

A graphene device including separated junction contacts and a method of manufacturing the same are disclosed. The graphene device is a field effect transistor (FET) in which graphene is used as a channel. A source electrode and a drain electrode do not directly contact the graphene channel, and junction contacts formed by doping semiconductor are separately disposed between the graphene channel and the source electrode and between the graphene channel and the drain electrode. Therefore, in an off state where a voltage is not applied to a gate electrode, due to a barrier between the graphene channel and the junction contacts, carriers may not move. As a result, the graphene device may have low current in the off state.

Graphene device including separated junction contacts and method of manufacturing the same

According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 10cm, and a depletion width of less than or equal to 3 nm.

Electronic device including graphene

A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.

Graphene devices and methods of fabricating the same

A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.

Memory devices including graphene switching devices

A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.

Three-dimensional graphene switching device

Graphene transferring members, graphene transferrer, methods of transferring graphene, and methods of fabricating a graphene device, may include a metal thin-film layer pattern and a graphene layer sequentially stacked on an adhesive member. The metal thin-film layer and the graphene layer may have the same shape. After transferring the graphene layer onto a transfer-target substrate during the fabrication of a graphene device, the metal thin-film layer is patterned to form electrodes on respective ends of the graphene layer by removing a portion of the metal thin-film layer.

Graphene-transferring member, graphene transferrer, method of transferring graphene, and methods of fabricating graphene device by using the same

A method of transferring graphene includes patterning an upper surface of a substrate to form at least one trench therein, providing a graphene layer on the substrate, the graphene layer including an adhesive liquid thereon, pressing the graphene layer with respect to the substrate, and removing the adhesive liquid by drying the substrate.

Method of transferring graphene using trench and substrate for receiving graphene

According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Field effect transistor using graphene

Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.

Inverter logic devices including graphene field effect transistor having tunable barrier

According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate.

Tunneling field-effect transistor including graphene channel

According to example embodiments, a graphene switching devices has a tunable barrier. The graphene switching device may include a gate substrate, a gate dielectric on the gate substrate, a graphene layer on the gate dielectric, a semiconductor layer and a first electrode sequentially stacked on a first region of the graphene layer, and a second electrode on a second region of the graphene layer. The semiconductor layer may be doped with one of an n-type impurity and a p-type impurity. The semiconductor layer may face the gate substrate with the graphene layer being between the semiconductor layer and the gate substrate. The second region of the graphene layer may be separated from the first region on the graphene layer.

Graphene switching device having tunable barrier

A method of preparing graphene includes forming a silicon carbide thin film on a substrate, forming a metal thin film on the silicon carbide thin film, and forming a metal composite layer and graphene on the substrate by heating the silicon carbide thin film and the metal thin film.

Growing community of inventors

Hwaseong-si, South Korea

Hyun-Jae Song