Skhynix Inc.

Hynix Semiconductor Inc.

Hyun Heo

Dong Hwan Lee

Min Gyu Koo

Yeonghun Lee

Hee Youl Lee

Sung Jae Chung

Sang Heon Lee

Hea Jong Yang

Yong Dae Park

Jeong Hyong Yi

A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array disposed on a substrate, a bit line connected to the memory cell array, a peripheral circuit disposed between the memory cell array and the substrate, the peripheral circuit including a transistor, a conductive line disposed between the memory cell array and the transistor, a lower connection structure connecting the conductive line and the transistor, and two or more upper connection structures connecting the bit line and the conductive line, the two or more upper connection structures being spaced apart from each other.

Semiconductor memory device with improved operation speed

A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.

Manufacturing method of semiconductor device including transistor having offset insulating layers

Semiconductor device including transistor having offset insulating layers

A semiconductor apparatus includes a voltage supply circuit suitable for outputting a high voltage, a transfer circuit coupled between the voltage supply circuit and a peripheral circuit and suitable for transferring the high voltage to the peripheral circuit and a transfer control circuit suitable for outputting a transfer control signal to the transfer circuit to control the transfer of the high voltage to the peripheral circuit, wherein the transfer control circuit outputs the transfer control signal having a first positive voltage level to a gate of a transistor included in the transfer circuit when the voltage supply circuit outputs the high voltage to the transfer circuit.

Semiconductor apparatus having transfer circuit transferring high voltage

This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor.

Non-volatile memory devices and methods of manufacturing the same

A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation.

3-dimensional semiconductor device having memory cells stacked over substrate

A semiconductor memory device includes a first memory block group including memory blocks coupled to first sub bit lines, a second memory block group including memory blocks coupled to second sub bit lines, an operation circuit coupled to main bit lines, and configured to perform an operation for data input/output to/from a memory block selected from the first memory block group or the second memory block group, and a bit line control circuit configured to differently control sub bit lines of the selected memory block group and sub bit lines of the unselected memory block groups in response to group select signals for selecting a memory block group including the selected memory block of the first memory block group and the second memory block group and voltages of the main bit lines controlled by the operation circuit.

Semiconductor memory device

A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.

Growing community of inventors

Seoul, South Korea

Hyun Heo