Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Other

Hyun Duk Kim

Scott J Norton

Meichun Hsu

Maria G Castellanos

Swapneel Kekre

Riddhiman Ghosh

Scott Alan Rhine

ChenXiang Zhai

An operating system provides instructions for execution by plural hardware threads of a multithreaded core of a processor, the plural hardware threads appearing as separate logical processors to the operating system. An abstraction layer converts respective identifiers of the plural hardware threads to a core identifier representing the core. The abstraction layer presents the core identifier to a user application to hide the plural hardware threads from the user application, and to present the core as a single-threaded core to the user application.

Abstracting a multithreaded processor core to a single threaded processor core

Causal topic mining can include incorporating non-text time series data with a number of articles based on a time relationship and analyzing the incorporated non-text time series data and the number of articles at a particular time to determine a causal relationship.

Causal topic miner

A method for generating summaries of text is described. The method includes the step of extracting features from text of text lists from summaries. The explanatoriness of the text is then evaluated, wherein evaluating the explanatoriness of text includes evaluating the features of the text, including at least the step of evaluating the discriminativeness of the features of the text by comparing the text to a first text data set, wherein the first text data set is derived from a topic label. The evaluated text is then ranked based on the explanatoriness evaluation.

Generation of explanatory summaries

In an embodiment of the invention, an apparatus and method to abstract a multithreaded processor core to single threaded processor core include performing the steps of: viewing, by an operating system, a first hardware thread and a second hardware thread in a processor core; and viewing, by a user application, the first hardware thread and the second hardware thread as a single CPU object.

An embodiment of the invention provides an apparatus and method for accurate measurement of utilizations in a hardware multithreaded processor core. The apparatus and method perform the acts including: determining idle time spent cycles which are cycles that are spent in idle by a hardware thread in a processor core; determining idle consumed cycles which are cycles that are consumed in the idle time spent cycles, by the hardware thread; and determining at least one of a processor core utilization and a logical processor utilization based upon at least one of the idle time spent cycles (d) and idle consumed cycles (d).

Accurate measurement of multithreaded processor core utilization and logical processor utilization

A determination of processor core utilization by a plurality of hardware threads over a time interval is made through a division of a length of the time interval by a total count of the plurality of hardware threads.

Hardware threads processor core utilization

In one embodiment, a method comprises (i) identifying a group associated with an executable that is using a resource of a computer system, (ii) decrementing a group utilization limit for the resource when the group utilization limit is greater than zero, (iii) decrementing a utilization reserve for the group when the group utilization limit for the resource equals zero, wherein operations (i)-(iii) are performed by a software routine responsive to system interrupts, and (iv) scheduling another executable to use the resource, wherein the scheduling verifies that (a) the another executable belongs to a group that has a non-zero group utilization limit for the resource or (b) the another executable belongs to a group that has a non-zero utilization reserve.

Controlling computer resource utilization

An arrangement, in a computer system, for coordinating scheduling of threads on a plurality of processor sets (PSETs). The arrangement includes a first processor set (PSET) having a first set of scheduling resources, the first set of scheduling resources. The arrangement further includes a second processor set (PSET) having a second set of scheduling resources. The first set of scheduling resources is configured to schedule threads assigned to the first PSET only among processors of the first PSET, and the second set of scheduling resources is configured to schedule threads assigned to the second PSET only among processors of the second PSET.

Per processor set scheduling

A method in a computer system for coordinating scheduling of threads among a plurality of processors. The method includes collecting, using a cooperative scheduling component (CSC), system data pertaining to the plurality of processors. The method further includes calculating, using the CSC, unified scheduling-related parameters (USRPs) from the system data. The method additionally includes furnishing the USRPs from the CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby at least two of the thread launcher, the thread balancer, and the thread stealer employ the USRPs to perform their respective scheduling-related tasks.

Adaptive cooperative scheduling

A computer-implemented method for traversing a first set of objects in a first dynamic list in a computer system. The method includes partitioning copies of the first set of objects into a plurality of second dynamic lists, each of the plurality of second dynamic lists being configured to contain a subset of the copies of the first set of objects, copies of the first set of objects being disposed in the plurality of second dynamic lists. The method also includes traversing the plurality of second dynamic lists using a plurality of traversal threads, thereby causing at least some of the copies of the first set of objects to be traversed in parallel.

Parallel traversal of a dynamic list

A card unit system comprising a combination of a postal communication and a detachable telephone calling card and a method for constructing and implementing such unit system which combines the benefits of telecommunication with postage and which optionally includes a gift certificate, coupon or a toll free number to access appropriate voice mail on a single unit.

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Champaign, IL, United States of America

Hyun Duk Kim