Samsung Electronics Co., Ltd.

Hyun-chul Yoon

Kyung-Ryun Kim

Woong-dai Kang

Young-Ho Kim

Seong-Jin Jang

Jong-Kyu Kim

Jung-Bae Lee

So-Young Kim

Young-Ju Kim

Soo-Young Kim

Jae-Youn Youn

Joo-sun Choi

Hyuk-Joon Kwon

Bok-Yeon Won

Yoon-jae Lee

Su-a Kim

Dong-Hak Shin

Sang-Jae Rhee

Jong-Min Oh

Kwang-Sook Noh

Soo-Hwan Kim

Sang-Keun Han

Sung-Gil Choi

Jin-yong Choi

Ji-Suk Kwon

Bum-Jae Lee

Sang-Dong Kwon

Hyuk-joon Kwon

Ji-Hak Yu

Seok-Jae Lee

Jang-Bin Yim

Min-Woo Won

A memory device including a memory cell array connected to a first bit line, first word lines, and second word lines, the memory cell array including a first memory cell and a second memory cell, the first memory cell being connected between the first word lines and the first bit line, and the second memory cell being connected between the second word line and the first bit line; a first word line driver configured to drive the first word lines; a second word line driver configured to drive the second word lines; and a test manager configured to drive second word lines to change a capacitance of the first bit line, and after the capacitance of the first bit line is changed, drive first word lines to test the first word lines.

Memory device performing test on memory cell array and method of operating the same

A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.

Semiconductor memory devices, methods of operating semiconductor memory devices and memory systems

A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

Memory device and method of disposing conduction lines of the same

A semiconductor memory device includes a memory cell array and a refresh control circuit. The refresh circuit is configured to: perform a second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation, and not perform the second burst refresh operation on the memory cell rows after the memory cell rows exit from a self refresh operation. Whether the refresh control circuit performs or does not perform the second burst refresh operation is based on a comparison between an entering time for the self refresh operation of the memory cell rows and a reference time.

Semiconductor memory device performing a refresh operation, and memory system including the same

A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.

Semiconductor memory devices having bit lines

Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.

Semiconductor devices having fuses and methods of forming the same

Growing community of inventors

Yongin-si, South Korea

Hyun-chul Yoon