Samsung Electronics Co., Ltd.

Hyun-Chul Yoon

Bong-Soo Kim

Jin-Young Kim

Nam-Gun Kim

Sung-Il Cho

Kwan-Sik Cho

Jihee Kim

Jin Su Park

Yoo-Sang Hwang

Je-min Park

Dongjun Shin

Kyoung-seon Kim

Younghan Kim

Hai-sub Na

Kukhan Yoon

Taeseop Choi

Kyu-Chang Kang

Jungheun Hwang

Seok-Hyun Lim

Joonghee Kim

Hyeon-Ok Jung

Hanseung Kwak

Seokhyun Lim

Yeong-Shin Park

Tae-Yong Song

Kichul Chun

Sungun Kwon

Donghak Shin

Jin Il Oh

Soonwon Hwang

Sunghoon Choi

Changyoung Lee

In a sense amplifier circuit, a first transistor is electrically connected between a first bitline and a first node, a first inverter includes a first input terminal and a first output terminal connected to the first node, and a second inverter includes a second input terminal connected to a second node and a second output terminal. A second transistor is electrically connected between the first output terminal and the second node, and a third transistor is electrically connected between the second output terminal and the first node. A precharge circuit transfers a first voltage to the first and second nodes during a first period, and transfers a second voltage higher than the first voltage to the first and second nodes during a second period.

Sense amplifier circuit with precharge, memory device including the same and sensing method of memory device

Disclosed are semiconductor devices and their fabrication methods. The method includes forming an etching target on a substrate including cell and key regions, forming lower and upper mask layers on the etching target, performing photolithography to form an upper mask pattern including a hole on the cell region, a preliminary key pattern on the key region, a bar pattern on the key region, and a trench between the preliminary key pattern and the bar pattern, forming pillar and dam patterns filling the hole and the trench, performing photolithography to remove the upper mask pattern except for the bar pattern, using the pillar pattern, the dam pattern, and the bar pattern as an etching mask to form a lower mask pattern, and using the lower mask pattern as an etching mask to form an etching target pattern on the cell region and a key pattern on the key region.

Method of fabricating semiconductor device using multipe photolithography for patterning

Disclosed is a method of fabricating a semiconductor device. The method comprises stacking an etching target layer, a first mask layer, an under layer, and a photoresist layer on a substrate, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, and performing a nitrogen plasma treatment on the photoresist pattern while using the first mask layer as an etching stop layer, the performing continuing until a top surface of the first mask layer is exposed. During the performing, the under layer is etched to form an under pattern below the photoresist pattern.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming a feature layer on a substrate, forming a plurality of reference patterns, arranged at a first pitch, on the feature layer, forming an organic liner on a side wall of each of the plurality of reference patterns, forming a plurality of buried patterns on the organic liner, removing the organic liner exposed between the plurality of buried patterns and the plurality of reference patterns, and etching the feature layer by using the plurality of buried patterns and the plurality of reference patterns as etch masks to form a feature pattern. Each of the plurality of buried patterns covers a space between side walls of two adjacent reference patterns among the plurality of reference patterns.

A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

Semiconductor devices including bit line contact plug and peripheral transistor

A method of fabricating a semiconductor device with conductive patterns comprises sequentially forming an etch-target layer and a middle mold layer on a substrate, forming a first upper mold pattern and a second upper mold pattern on the middle mold layer to have top surfaces at different levels, etching the middle mold layer using the first and second upper mold patterns as an etch mask to form first and second middle mold patterns, respectively, forming a third middle mold pattern between the first and second middle mold patterns, and etching the etch-target layer using the first to third middle mold patterns as an etch mask to form conductive patterns.

Methods of fabricating semiconductor devices

An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.

Methods of forming electronic devices having pads using first and second masks

A semiconductor memory device is provided. A cell array includes a DRAM cell connected to one of a pair of bit lines. A bit line sense amplifier is coupled to the pair of bit lines. The bit line sense amplifier discharges a low-level bit line of the pair of bit lines toward a ground level and clamps the low-level bit line to a boosted sense ground voltage in response to a control signal. A sense amplifier control logic generates the control signal having a pulse interval. The low-level bit line is discharged toward the ground level for the pulse interval and after the pulse interval ends, the low-level bit line is clamped to the boosted sense ground voltage.

Semiconductor memory device and sense amplifier control method thereof

Semiconductor devices including bit line contact plug and peripheral transitor

Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same

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Seongnam-si, South Korea

Hyun-Chul Yoon