Hynix Semiconductor Inc.

Yonsei University

Skhynix Inc.

Hyun Chul Sohn

Se Aug Jang

Sang Tae Ahn

Soo Hyun Kim

Jun Ki Kim

Dong Sun Sheen

Ki Seon Park

Seok Pyo Song

Jae Sung Roh

Hee Do Na

Sung Woong Chung

Hyung Soon Park

Young Mo Kim

Yong Soo Kim

Hyeon Ju An

Jae Geun Oh

Min Suk Lee

Sang Ick Lee

Jong Chae Kim

Kyung Dong Yoo

Deok Sin Kil

Do Hwan Kim

Jae Sung Rohh

Provided are a 3-dimensional non-volatile memory device and a method of fabricating the same. The 3-dimensional non-volatile memory device may include a substrate; semiconductor pillars, which are arranged at a certain interval in a first direction and a second direction different from the first direction; a string isolation film, which is arranged between the semiconductor pillars arranged in the first direction among the semiconductor pillars and extends in the first direction and a third direction vertical to the main surface of the substrate; first sub-electrodes repeatedly stacked on the substrate in the third direction; second sub-electrodes, which are electrically isolated from the first sub-electrodes by the string isolation film, and are repeatedly stacked on the substrate in the third direction; and information storage films including a first information storage film and a second information storage film.

3-dimensional non-volatile memory device and method of fabricating the same

An image sensor includes a pixel layer in which an active pixel array and an optical black pixel array are formed; a first anti-reflective layer which is formed over the active pixel array, and including a hafnium oxide layer with a high transmittance; and a second anti-reflective layer which is formed over the optical black pixel array, and including a hafnium oxide layer with a low transmittance.

Image sensor having anti-reflective layer and fabricating method thereof

Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.

Recessed gate electrode MOS transistor and method for fabricating the same

A fin transistor is formed by forming a hard mask layer on a substrate having an active region and a field region. The hard mask layer is etched to expose the field region. A trench is formed by etching the exposed field region. The trench is filled with an SOG layer. The hard mask layer is removed to expose the active region. An epi-silicon layer is formed on the exposed active region. The SOG layer is then partially etched from the upper end of the trench, thus filling a lower portion of the trench. A HDP oxide layer is deposited on the etched SOG layer filling the trench, thereby forming a field oxide layer composed of the SOG layer and the HDP oxide. The HDP oxide layer in the field oxide layer is etched to expose both side surfaces of the epi-silicon layer. A gate is then formed on the epi-silicon layer of which both side surfaces are exposed and the field oxide layer.

Method of forming fin transistor

Disclosed is a method for forming a capacitor of a semiconductor device. In such a method, a mold insulating layer is formed on an insulating interlayer provided with a storage node plug, and the mold insulating layer is etched to form a hole through which the storage node plug is exposed. Next, a metal storage electrode with an interposed WN layer is formed on a hole surface including the exposed storage node plug and the mold insulating layer is removed. Finally, a dielectric layer and a plate electrode are formed in order on the metal storage electrode.

Method for forming capacitor of semiconductor device

A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.

Transistor structure of memory device and method for fabricating the same

A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.

Method of manufacturing semiconductor device for formation of pin transistor

Disclosed is a method for forming a capacitor of a semiconductor device, which can improve a leakage current characteristic in applying HfxAlyOz as a dielectric film. In such a method, HfxAlyOz thin films are deposited on a storage electrode to form an HfxAlyOz dielectric film and a plate electrode is formed on the dielectric film. The HfxAlyOz dielectric film consists of laminated HfxAlyOz thin films which are different in compositions of Hf and Al such that the lower HfxAlyOz thin film adjoining the storage electrode has a larger composition ratio of Al than that of Hf and the upper HfxAlyOz thin film has a larger composition ratio of Hf than that of Al, and the upper HfxAlyOz thin film is subjected to heat treatment under an oxygen atmosphere after its deposition.

Disclosed is a method for forming a polysilicon plug of a semiconductor device. The method comprises the steps of: forming a stacked pattern of a wordline and a hard mask film on a semiconductor substrate comprising a cell region and a peripheral circuit region; forming a spacer on a sidewall of the stacked pattern; forming an interlayer insulating film on the semiconductor substrate; polishing the interlayer insulating film via a CMP process using the hard mask film as a polishing barrier film; forming a barrier film on the semiconductor substrate including the interlayer insulating film; selectively etching the barrier film and the interlayer insulating film to form a landing plug contact hole; depositing a polysilicon film filling the landing plug contact hole on the semiconductor substrate; blanket-etching the polysilicon film using the barrier film as an etching barrier film; and polishing the polysilicon film and the barrier film using the hard mask film as a polishing barrier film to form a polysilicon plug.

Method for forming polysilicon plug of semiconductor device

A method for fabricating an isolation layer in a semiconductor device is disclosed. The disclosed method comprises steps of: forming a trench on a semiconductor substrate; forming a flowing insulating layer within the trench; making the insulating layer precise; and forming a precise insulating layer over an upper surface of the whole structure on which the flowing insulating layer is formed. According to the method of fabricating an isolation layer in a semiconductor device, occurrence of fine pores at adjacent active regions of sidewalls in a trench can be prevented.

Growing community of inventors

Seoul, South Korea

Hyun Chul Sohn