Skhynix Inc.

Hyun Chul Seo

Seung Hwan Kim

Hyeong Seok Choi

Jun Sik Kim

Moon Un Hyun

Ki Young Kim

Jong Hyun Kim

Jae Min Kim

Seung Yeop Lee

Il Hwan Cho

Shin Young Park

Hee Ra Roh

Seang Hwan Kim

Dong Hwan Seol

A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Semiconductor chip including through electrode, and semiconductor package including the same

A semiconductor device includes a first redistribution layer pattern, a second redistribution layer pattern, and a recognition mark. The first redistribution layer pattern is formed on a semiconductor substrate. The second redistribution layer pattern, with a bonding pad portion, is disposed on the first redistribution layer pattern. Furthermore, the recognition mark is formed on the first redistribution layer pattern to indicate a position of the bonding pad portion.

Semiconductor devices including recognition marks

A semiconductor package includes: a substrate; a first semiconductor chip positioned over the substrate and electrically connected to the substrate; a second semiconductor chip stack positioned over the first semiconductor chip and including a plurality of second semiconductor chips that are stacked in a vertical direction while being electrically connected to the first semiconductor chip; and a dummy third semiconductor chip positioned over the second semiconductor chip stack, wherein a third height of a third bonding structure coupling the third semiconductor chip to an uppermost second semiconductor chip among the second semiconductor chips is greater than a second height of a second bonding structure coupling one among the second semiconductor chips to an another one among the second semiconductor chips positioned directly therebelow or the first semiconductor chip positioned directly therebelow.

Semiconductor package including stacked semiconductor chips

A method of manufacturing a semiconductor package includes mounting a first semiconductor chip and a second semiconductor chip on a substrate, forming a first film on a top surface of the first semiconductor chip, and loading the first semiconductor chip and the second semiconductor chip mounted on the substrate between a lower mold frame and an upper mold frame. The method further includes providing a molding material between the lower mold frame and the upper mold frame, removing the lower mold frame and the upper mold frame, and removing the first film on the top surface of the first semiconductor chip to expose the top surface of the first semiconductor chip.

Semiconductor packages including different type semiconductor chips having exposed top surfaces and methods of manufacturing the semiconductor packages

A semiconductor package includes a semiconductor chip and a package substrate. The semiconductor chip is mounted on the package substrate. The package substrate includes a dielectric layer through which a vent hole penetrates, trace patterns disposed on the dielectric layer, and a protecting block disposed between the trace patterns and the vent hole.

Semiconductor package and package substrate including vent hole

A semiconductor device includes: a lower structure; a redistribution insulating layer disposed over the lower structure; a redistribution conductive layer disposed over the redistribution insulating layer and electrically connected to a part of the lower structure, the redistribution conductive layer including a redistribution pad; and a protective layer covering the redistribution insulating layer and the redistribution conductive layer while leaving the redistribution pad exposed. The redistribution conductive layer includes a trench disposed adjacent to the redistribution pad, and a part of the protective layer fills the trench.

Semiconductor device including redistribution layer and method for fabricating the same

A semiconductor package includes a semiconductor chip with a normal connection electrode and a measurement connection electrode, formed on a first surface, and a substrate with a normal substrate pad, connected to the normal connection electrode, and a measurement substrate pad, connected to the measurement connection electrode. The normal substrate pad and the measurement substrate pad are formed on a surface that faces the first surface. The measurement connection electrode includes first and second edge measurement connection electrodes and first and second center measurement connection electrodes. The measurement substrate pad includes a center measurement substrate pad, a first edge measurement substrate pad, and a second edge measurement substrate pad. The first edge measurement connection electrode and the first center measurement connection electrode are electrically connected to each other, and the second edge measurement connection electrode and the second center measurement connection electrode are electrically connected to each other.

Semiconductor package

A semiconductor wafer includes a first chip region and a second chip region spaced apart from each other by a scribe lane region. The semiconductor wafer also includes a test pad disposed in the scribe lane region. The semiconductor wafer additionally includes a protective layer partially covering the first chip region, the second chip region, and the scribe lane region, wherein the protective layer covers a portion of the test pad adjacent to the first chip region and leaves a remaining portion of the first test pad exposed.

Semiconductor wafer, method for separating the semiconductor wafer, semiconductor chip, and semiconductor package including the semiconductor chip

A semiconductor package includes: a package substrate; a first semiconductor chip disposed over the package substrate and having a center region and an edge region; and a package redistribution layer disposed over the first semiconductor chip, wherein the first semiconductor chip comprises: a lower structure; a redistribution conductive layer disposed over the lower structure and electrically connected to the lower structure, the redistribution conductive layer including a redistribution pad disposed in the center region; and a protective layer covering the lower structure and the redistribution conductive layer, and having an opening exposing the redistribution pad, wherein the package redistribution layer comprises: a package redistribution conductive layer connected to the redistribution pad and extending to the edge region, the package redistribution conductive layer including a package redistribution pad disposed in the edge region, and, wherein, in the edge region, the redistribution conductive layer is omitted.

Semiconductor package including a semiconductor chip having a redistribution layer

A method of fabricating a semiconductor package may include forming a plating layer on a surface of a substrate body. A circuit resist pattern and a monitoring resist pattern may be formed on the plating layer, and the plating layer may be etched using the circuit resist pattern and the monitoring resist pattern as etch masks, thereby forming circuit patterns and sub-patterns of a monitoring pattern. A residual rate of the circuit patterns may be monitored by inspecting the number of the sub-patterns of the monitoring pattern remaining on the substrate body after an etch process for forming the circuit patterns and the sub-patterns of the monitoring pattern. A semiconductor chip may be bonded to the circuit patterns using inner connectors.

Methods of fabricating semiconductor packages including circuit patterns

A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines. The redistribution pads includes shared redistribution pads electrically coupled in common to the redistribution lines electrically coupled to the bonding pads of the first semiconductor chip and the redistribution lines electrically coupled to the bonding pads of the second semiconductor chip; and individual redistribution pads individually electrically coupled to the redistribution lines which are not electrically coupled with the shared redistribution pads.

Semiconductor chip module and semiconductor package including the same

A semiconductor device includes, a semiconductor chip having a first surface over which bonding pads are positioned, a second surface which faces away from the first surface, and a plurality of signal lines formed over the first surface, extending in a first direction; a plurality of redistribution lines formed over the first surface, having one set of ends electrically coupled to the bonding pads of the semiconductor chip, and extending in a direction oblique to the first direction; and a plurality of redistribution pads disposed over the first surface, and electrically coupled with an other set of ends of the redistribution lines which face away from the one set of ends.

Semiconductor device with decreased overlapping area between redistribution lines and signal lines

A semiconductor device includes a semiconductor chip and an inner interconnection structure. The semiconductor chip includes a front surface that exposes first connection terminals and a rear surface that is opposite to the front surface and exposes second connection terminals separated from the first connection terminals. The inner interconnection structure includes horizontal buried conductive lines and vertical connection lines disposed to pierce the semiconductor chip to connect the first connection terminals and the second connection terminals.

Semiconductor device including inner interconnection structure able to conduct signals or voltages in the semiconductor chip with vertical connection vias and horizontal buried conductive lines

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Icheon-si, South Korea

Hyun Chul Seo