Electronics and Telecommunications Research Institute

Hyun Cheol Bae

Sang Hun Kim

Sang Heung Lee

Seung Yun Lee

Jin Yeong Kang

Provided are a SiGe semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buried collector by doping impurity ions into a buried collector region formed on a substrate; forming a collector layer which is an active region and a collector electrode region by forming a Si epitaxial layer on the substrate having the buried collector; forming an isolation layer on the substrate and exposing the collector layer and the collector electrode region; forming a collector pad oxide layer on the collector electrode region; stacking a base epitaxial layer and a pad oxide layer on the substrate having the collector pad oxide layer and patterning the pad oxide layer; forming a first polycrystalline Si (poly-Si) layer on the patterned pad oxide layer; exposing at least a portion of the patterned pad oxide layer by etching the first poly-Si layer; depositing a metal layer on the first poly-Si layer to form a first silicide layer; forming an oxide layer on the substrate having the first silicide layer, and exposing a base-emitter junction and the collector electrode region; forming an emitter electrode and a collector electrode by depositing a second poly-Si layer on the exposed base-emitter junction and collector electrode region; and depositing a metal layer on the emitter and collector electrodes to form a second silicide layer, and forming a base terminal, an emitter terminal, and a collector terminal. In this method, base parasitic resistance can be reduced, an electrical short due to agglomeration caused by Ge can be prevented during the formation of the silicide layer, and the base-emitter junction can be protected using the pad oxide layer from external processes, thereby enhancing process stability and reliability.

SiGe semiconductor device and method of manufacturing the same

A germanium semiconductor device and a method of manufacturing the same are provided. The method includes the steps of: forming an isolation layer on a substrate using a shallow trench; forming a silicon-nitride layer on the substrate, and selectively etching the silicon nitride layer to expose source and drain regions; injecting impurities onto a surface of the substrate over the exposed source and drain regions using delta-doping to form a delta-doping layer; selectively growing a silicon germanium layer containing impurities on the delta-doping layer; rapidly annealing the substrate and forming source and drain regions by diffusion of the impurities; depositing an insulating layer on the entire surface of the substrate; etching the insulating layer and forming source and drain contact parts to be in contact with source and drain terminals; depositing metal over the insulating layer having the source and drain contact parts thereon and forming a metal silicide layer; and after forming the silicide layer, forming the source and drain terminals to be in contact with the silicide layer. Accordingly, the source and drain regions having a shallow junction depth may be ensured by forming the source and drain regions through annealing after delta-doping and selectively growing the silicon germanium layer containing high-concentration impurities. Also, the germanium silicide layer is stably formed by the silicon germanium layer grown in the source and drain regions, and thus contact resistance is lowered and driving current of the device is improved.

Germanium semiconductor device and method of manufacturing the same

Provided are a semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a first silicon layer on a semiconductor substrate; patterning the first silicon layer formed on the semiconductor substrate, and exposing a channel region; forming a second silicon layer on the semiconductor substrate in which the channel region is exposed; removing the first silicon layer, and forming source and drain regions; and forming a third silicon layer in the source and drain regions. According to the manufacturing method, it is possible to minimize defects in a silicon interface by forming the source and drain using only a selective epitaxial growth method without a dry-etching process. Also, since stress is concentrated to a silicon channel region, hole mobility and driving current characteristics are considerably improved.

Semiconductor device and method of manufacturing the same

Provided is a method of fabricating a silicon germanium (SiGe) Bi-CMOS device. In the fabrication method, the source and drain of the CMOS device is formed using a silicon germanium (SiGe) heterojunction, instead of silicon, thereby preventing a leakage current resulting from a parasitic bipolar operation. Further, since the source and drain is connected with an external interconnection through the nickel (Ni) silicide layer, the contact resistance is reduced, thereby preventing loss of a necessary voltage for a device operation and accordingly, making it possible to enable a low voltage and low power operation and securing a broad operation region even in a low voltage operation of an analogue circuit.

Growing community of inventors

Daejeon, South Korea

Hyun Cheol Bae