Seoul National University

Hyun Bin Lee

Won Young Lee

Proposed is an apparatus for a digital clock and data recovery. The apparatus includes a frequency detector for detecting a high frequency (FH) signal, a low frequency (FL) signal and ultra-high frequency (FUH) signal by determining the relationship between an input data rate and a clock frequency, and generating a continuous frequency up (CFUP) signal and a continuous frequency down (CFDN) signal based on the FH, FL and FUH signals; and a digital loop filter (DLF) for controlling to adjust a clock frequency in a coarse adjustment stage using the CFUP and CFDN signals and to adjust a clock frequency in a fine adjustment stage using the FH and FL signals.

Growing community of inventors

Seoul, South Korea

Hyun Bin Lee