Korea Electronics Technology Institute

Hyun Bean Yi

Young Hwan Kim

Chang Won Park

Jae Gi Son

Ki Man Jeon

Sung Ju Park

An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.

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Kyunggi-do, South Korea

Hyun Bean Yi