Hyundai Mobis Co., Ltd.

Hyundai Autron Company Ltd.

Magnachip Semiconductor, Inc.

Dongbu Hitek Co., Ltd.

Hyundai Motor Company

Hyuk Woo

Ju Hwan Lee

Young Joon Kim

Jeong Mok Ha

Sin A Kim

Tae Youp Kim

Tae Young Park

Chang Yong Choi

Moon Soo Cho

Han Sin Cho

Soon Tak Kwon

Kwang Yeon Jun

Tae Yeop Kim

Tae Yang Kim

Min Gi Kang

Dae Byung Kim

Dae Hwan Chun

Youngkyun Jung

Jongseok Lee

Youngjoon Kim

Chang-sik Lim

Seong-hwan Yun

Seong Hwan Yun

Seon-hyeong Jo

Kwang-yeon Jun

Dong Hwan Choi

Moon-soo Cho

Taeyeop Kim

Yoon Chul Choi

Ki Tae Kang

Seon Hyeong Jo

A power semiconductor device includes an SiC semiconductor layer, a plurality of well regions disposed in the semiconductor layer such that two adjacent well regions at least partially make contact with each other, a plurality of source regions on the plurality of well regions in the semiconductor layer, a drift region in a first conductive type, a plurality of trenches recessed into the semiconductor layer from the surface of the semiconductor layer, a gate insulating layer on an inner wall of each trench, a gate electrode layer disposed on the gate insulating layer and including a first part disposed in each trench and a second part on the semiconductor layer, and a pillar region positioned under the plurality of well regions to make contact with the drift region and the plurality of well regions in the semiconductor layer, and having a second conductive type.

Power semiconductor device and method for fabricating the same

A power semiconductor device includes a plurality of gate electrodes configured to be recessed from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, the second surface being opposite to the first surface, an emitter region configured to make contact with a trench and the first surface, being provided between respective ones of the plurality of gate electrodes, and including impurities of a first conductive type, a collector region configured to make contact with the second surface, and including second impurities of a second conductive type opposite to the first conductive type, a floating region extending toward the second surface in an extension direction of the trench while surrounding a bottom surface of the trench, and including the second impurities, and a trench emitter region interposed between the plurality of gate electrodes in the trench.

Power semiconductor device, power semiconductor chip including the same, and method for manufacturing the same

A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

Power semiconductor device and method of fabricating the same

A power semiconductor device includes a substrate, including an active region and edge regions, including a semiconductor layer of a first conductive type including silicon carbide (SiC); an insulating film disposed on the edge regions; a field plate pattern disposed on the insulating film; a first doped region of a second conductive type disposed inside the substrate to extend downward from a top surface of the edge regions; a second doped region of the second conductive type, buried in the edge regions, extends in a direction having a vector component parallel to the top surface of the substrate; and a third doped region of the first conductive type is disposed on the second doped region and at a side portion of the first doped region.

Power semiconductor device

A power semiconductor device according to an aspect of the present disclosure includes a semiconductor layer of silicon carbide (SiC), a plurality of well regions that is disposed in the semiconductor layer, spaced from each other and has a second conductivity type, a plurality of source regions that are disposed in the semiconductor layer on the plurality of well regions respectively, spaced from each other, a drift region that has the first conductivity type and is disposed in the semiconductor layer, the drift region extending from a lower side of the plurality of well regions to a surface of the semiconductor layer through between the plurality of well regions, a plurality of trenches, a gate insulating layer, and a gate electrode layer that is disposed on the gate insulating layer.

A power semiconductor device includes a semiconductor layer of SiC, a gate insulating layer, a gate electrode layer, a drift region including at least one protruding portion in the semiconductor layer and having a first conductivity type, a well region including a first well region in the semiconductor layer and in contact with the protruding portion, and a second well region in the semiconductor layer outside the gate electrode layer and connected to the first well region, and having a second conductivity type, a source region including a first source region in the first well region and a second source region in the second well region and connected to the first source region, and having the first conductivity type, and a channel region under the gate electrode layer, in the semiconductor layer between the protruding portion and the first source region, and having the first conductivity type.

Provided is a semiconductor device. The device comprises an epitaxial layer that constitutes a part of an active cell region and is doped with impurities of a first conductivity type at a first concentration; a field stop region that is located below the epitaxial layer and doped with impurities of a second conductivity type at a second concentration which are then activated; and a collector region that is located below the field stop regionand is doped with impurities of a second conductivity type. The field stop region is formed by repeatedly alternately arranging regions in which the activation of the impurities of the first conductivity type is relatively strong and regions in which the activation of the impurities of the first conductivity type is relatively weak.

The power semiconductor device includes: a first trench gate and a second trench gate in a stripe shape extending in one direction in parallel and spaced apart from each other in a substrate; a third trench gate in a ladder shape extending in a direction different from the one direction between the first trench gate and the second trench gate in the substrate; a first conductive type body area each disposed between the first trench gate, the second trench gate and the third trench gate, respectively, in the substrate; a pair of first conductive type floating first areas surrounding each of bottom surfaces and at least one side of the first trench gate and the second trench gate in the substrate; and a first conductive type floating second area surrounding a bottom surface of the third trench gate in the substrate.

Power semiconductor device and manufacturing method thereof

The present invention provides a semiconductor device comprising a substrate including an active region and an edge region and containing a semiconductor doped with impurities having a first conductivity type; an insulating film disposed on the edge region of the substrate; a field plate pattern disposed on the insulating film; and at least one first doped region having a second conductivity type buried in the edge region of the substrate and extending in a direction having a vector component parallel to an upper surface of the substrate.

Provided is a power semiconductor device comprising a gate electrode in a trench of a substrate; a body region having a first conductivity type on one side of the gate electrode; a source region having a second conductivity type adjacent to the gate electrode; a floating region having a first conductivity type on the other side of the gate electrode; an edge doped region having a first conductivity type spaced apart from the floating region and electrically connected to the source region; an edge junction isolation region having a second conductivity type between the floating region and the edge doped region; and a drift region having a second conductivity type below the floating, edge doped, and edge junction isolation regions, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region.

A semiconductor device includes: an n&#x2212; type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench formed in the n&#x2212; type layer; a p type region disposed on both side surfaces of the first trench; an n+ type region disposed on both side surfaces of the first trench and disposed on the n&#x2212; type layer and the p type region; a gate insulating layer disposed inside the first trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ region; and a drain electrode disposed on the second surface of the n+ type silicon carbide substrate, wherein a first channel as an accumulation layer channel and a second channel as an inversion layer channel are disposed in both side surfaces of the first trench, and the first channel and the second channel are disposed to be adjacent in a horizontal direction for the first surface of the n+ type silicon carbide substrate.

Semiconductor device comprising accumulation layer channel and inversion layer channel

Provided are a semiconductor device, the semiconductor device comprise, a substrate which comprises a first surface and a second surface facing the first surface, an epitaxial layer which is formed on the first surface of the substrate and has a first conductivity type, a base region which is formed in the epitaxial layer and has a second conductivity type different from the first conductivity type, a source region which is formed in the base region and has the first conductivity type, a channel region which is formed in the base region to bc separated from the source region and has the first conductivity type and a barrier region which is formed between the source region and the channel region and has the second conductivity type.

Semiconductor device and method of fabricating the same

Provided is a power semiconductor device comprising a pair of gate electrodes respectively disposed in a first trench and a second trench spaced apart from each other in a substrate; a body region having a first conductivity type disposed between the first trench and the second trench; a pair of floating regions having a first conductivity type spaced apart from each other and surrounding a bottom surface and at least one side surface of the first trench and the second trench, respectively; and a drift region having a second conductivity type which extends from below the pair of floating regions through a region between the pair of floating regions to the body region, wherein, in the drift region, the doping concentration of a second conductivity type between the pair of floating regions is higher than the doping concentration of a second conductivity type below the pair of floating regions.

Provided is a super junction semiconductor device. The super junction semiconductor device includes a vertical pillar region located in an active region and horizontal pillar regions located in a termination region that are connected with each other while simultaneously not floating the entire pillar region in the termination region. Thus, a charge compensation difference, generated among pillar regions, is caused to be offset, although the length of the termination region is relatively short.

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Incheon, South Korea

Hyuk Woo