Samsung Electronics Co., Ltd.

Hyuk Kim

Gang Zhang

Sung Il Cho

Sangwuk Park

Yong-Hyun Kwon

Dae Hyun Jang

Jae-ho Min

Yeongeun Yook

Kyoung Sub Shin

Seung Pil Chung

Sang Wuk Park

Edward Sung

Jongchul Park

Jong-Kyu Kim

Jinyoung Park

Sung-Il Cho

Seung-Pil Chung

Daehyun Jang

Jeon Il Lee

Seung Bo Shim

Han-Na Cho

Jin Young Bang

Jae Myung Choe

Yejeong Seo

Seong Wook Cheong

Eun Seon Lim

Sung Ii Cho

Sano Jin Choi

Byung Il Ahn

Joong He Lee

Chong Uck Kim

Jong-Kyoung Park

Seung-pil Chung

Sun Taek Lim

A semiconductor device and an electronic system including the same are provided. The semiconductor device may include a stacked structure including electrodes stacked on a substrate, interlayer insulating layers interposed between the electrodes, and an upper insulating layer covering the uppermost electrode among the electrodes, and a vertical structure passing through the stacked structure in a vertical direction, and each of the interlayer insulating layers may have a first thickness, and the upper insulating layer may have a second thickness greater than the first thickness, and the upper insulating layer may include an insulating material different from an insulating material of each of the interlayer insulating layers.

Semiconductor device and electronic system including the same

A semiconductor device includes a substrate, a data storage structure on the substrate, an insulating structure spaced apart from the data storage structure on the substrate, conductive lines spaced apart from each other and stacked in a vertical direction between the data storage structure and the insulating structure, active layers spaced apart from each other and stacked in the vertical direction between the data storage structure and the insulating structure, and intersecting the conductive lines, and a conductive pattern between the insulating structure and the active layers, and electrically connected to the active layers. The insulating structure includes first insulating patterns spaced apart from each other in a first horizontal direction, and a second insulating pattern between the first insulating patterns. The conductive pattern is between the second insulating pattern and the active layers. The second insulating pattern includes a material different from that of the first insulating patterns.

Semiconductor device

A semiconductor device includes a lower structure including lower wirings. A horizontal wiring layer is disposed on the lower structure while including a horizontal conductive layer, and a horizontal insulating layer extending through the horizontal conductive layer. A stack structure is disposed on the horizontal wiring layer. A channel structure extending into the horizontal wiring layer while extending through the stack structure is provided. A through electrode connected to the lower wirings while extending through the stack structure and the horizontal insulating layer is provided. The stack structure includes insulating layers and electrode layers repeatedly alternately stacked, and an interlayer insulating layer disposed at side surfaces of the insulating layers and the electrode layers. The through electrode includes a first portion extending into the interlayer insulating layer, and a second portion disposed between the first portion and the lower wirings while having a smaller horizontal width than the first portion.

Semiconductor device including channel structure and through electrode, electronic system, and method of forming the same

A showerhead according to an embodiment of the present inventive concept includes an upper plate including a plurality of gas supply passages, a lower plate including a plurality of supply holes and a plurality of exhaust slots formed in a lower surface, and a plurality of partition walls between the upper plate and the lower plate, connected to a plurality of exhaust slots and defining exhaust passages that are open at a side portion of the showerhead.

Showerhead and substrate processing apparatus

Shrouds and substrate treating systems including the same are provided. Substrate treating systems may include a process chamber, a supporter, and a plasma source that is spaced apart from the supporter in a vertical direction. The substrate treating systems may also include a shroud configured to contain the plasma therein. The shroud may include a sidewall portion and a first flange portion extending horizontally from the sidewall portion and including a plurality of first slits that extend through a thickness of the first flange portion. The first flange portion may define a first opening, and a portion of the supporter may extend through the first opening. The sidewall portion may include a plurality of second slits, and each of the plurality of second slits may extend through a thickness of the sidewall portion and may extend from one of the plurality of first slits toward the plasma source.

Shrouds and substrate treating systems including the same

Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.

Plasma treatment apparatus and method of fabricating semiconductor device using the same

A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.

Vertical memory device

An ion beam etching device comprises: an ion source configured to generate ions; a grid on a side of the ion source, the grid configured to accelerate the generated ions to generate an ion beam; a process chamber configured to have an etching process using the ion beam performed therein; and a variable magnetic field application part adjacent to the process chamber, the variable magnetic field application part configured to apply a variable magnetic field.

Ion beam etching devices

Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

Semiconductor memory devices

A semiconductor device includes gate stacks disposed on a substrate and spaced apart from each other in a first direction, with a separation region interposed between the gate stacks; channel regions penetrating through the gate stacks and disposed within each of the gate stacks; and a guide region adjacent to the separation region, penetrating through at least a portion of the gate stack, and having a bent portion that is bent toward the separation region.

Semiconductor chips are provided. A semiconductor chip includes a peripheral circuit region on a substrate. The semiconductor chip includes a semiconductor layer on the peripheral circuit region. The semiconductor chip includes a cell region on the semiconductor layer. Moreover, the semiconductor chip includes a layer/connector that is adjacent the semiconductor layer. Methods of manufacturing semiconductor chips are also provided.

Semiconductor chips and methods of manufacturing the same

A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines.

Vertical memory devices and methods of manufacturing the same

A semiconductor device includes a substrate having an upper surface extended in first and second directions perpendicular to each other, gate stack portions spaced apart from each other in the first direction, the gate stack portions including gate electrodes spaced apart from each other in a direction perpendicular to the an upper surface of the substrate and having lateral surfaces extended in the second direction to have a zigzag form, channel regions penetrating through the gate stack portions and disposed to form columns having a zigzag form in the second direction, at least two channel regions among the channel regions being linearly arranged in the first direction within the respective gate stack portion, and a source region disposed between the gate stack portions adjacent to each other and extended in the second direction to have a zigzag form.

Growing community of inventors

Seongnam-si, South Korea

Hyuk Kim