Intel Corporation

Hyuk Ju Ryu

Charles Henry Wallace

Rui Ma

Mark Armstrong

Mohit K Haran

Andy Chih-Hung Wei

Ayan Kar

Kalyan C Kolluru

Guillaume Bouche

Nicholas A Thomson

Zhiyong Ma

Akm A Ahsan

Changyok Park

Xianghong Tong

May Ling Oh

Sameer Jayanta Joglekar

Wen-Hsien Chuang

Hasan Faraby

Sayan Saha

Ira Jewell

Shuai Zhao

Charles Peterson

Jennifer Huening

Martin Von Haartman

Prasoon Joshi

Pulsed beam prober systems, devices, and techniques are described herein related to providing a beam detection frequency that is less than a electrical test frequency. An electrical test signal at the electrical test frequency is provided to die under test. A pulsed beam is applied to the die such that the pulsed beam has packets of beam pulses or a frequency delta with respect to the electrical test frequency. The packets of beam pulses or the frequency delta elicits a detectable beam modulation in an imaging signal reflected from the die such that the imaging signal is modulated at a detection frequency less than the electrical test frequency.

Stroboscopic electron-beam signal image mapping

Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

Transistor arrangements with stacked trench contacts and gate straps

Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Field-effect transistors with dual thickness gate dielectrics

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Portland, OR, United States of America

Hyuk Ju Ryu