Samsung Electronics Co., Ltd.

Hyuk-Ju Ryu

Hee-Sung Kang

Jong-hyon Ahn

Young-Wug Kim

You-Seung Jin

Jong-Hyon Ahn

Chang-Bong Oh

Mu-kyeng Jung

Kyung-soo Kim

Woo-young Chung

In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof

In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance

A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.

CMOS device with improved performance and method of fabricating the same

A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

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Seoul, South Korea

Hyuk-Ju Ryu