Apple Inc.

Hyuck-Jae Lee

Yafei Bi

Joshua P De Cesare

Mohammad Bagher Vahid Far

Sreeraman Anantharaman

Venu Madhav Duggineni

Lei He

Mir Bahram Ghaderi

Vanessa Cristina Heppolette

Vincent Wang

Hung Sheng Lin

Hyunwoo Nho

Kingsuk Brahma

Jie Won Ryu

Sun-il Chang

Baris Cagdaser

Junhua Tan

Jesse Aaron Richmond

Injae Hwang

Luigi Panseri

Toshiaki Sawada

Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.

Methods and apparatus for multi-lane mapping, link training and lower power modes for a high speed bus interface

Systems, methods, and apparatus to transition a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.

Low power display on mode for a display device

An electronic device includes a display having a number of pixels, source driving circuitry that drives data to the pixels, and data lines that communicatively couple the source driving circuitry with the pixels. The electronic device also includes quality monitoring and calibration circuitry that identifies degradation in the source driving circuitry, one or more of the data lines, or both. The electronic device may be controlled based at least in part upon identification of the degradation.

Display quality monitoring and calibration

This application relates to systems, methods, and apparatus for transitioning a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.

Growing community of inventors

San Francisco, CA, United States of America

Hyuck-Jae Lee