Samsung Electronics Co., Ltd.

Hyoungyol Mun

Sungdong Cho

Youngmin Lee

Kwangwuk Park

Seokhwan Jeong

Yoosang Hwang

Kiseok Lee

Sangjun Park

Eun-Ji Kim

Jong-Ho Moon

Inyoung Lee

Sangyeon Han

Seungjae Jung

Eunji Kim

Wonhee Cho

Kyuha Lee

Taehyun An

Hyungeun Choi

Minsung Kang

Han-Sik Yoo

Uidam Jung

A semiconductor device includes a semiconductor substrate including a first region and a second region, first metal lines spaced apart from each other at a first interval on the first region, second metal lines spaced apart from each other at a second interval on the second region, the second interval being less than the first interval, and a passivation layer on the semiconductor substrate and covering the first and second metal lines, the passivation layer including sidewall parts covering sidewalls of the first metal lines and the second metal lines, the sidewall parts including a porous dielectric layer, upper parts covering top surfaces of the first metal lines and the second metal lines, and an air gap defined by the sidewall parts between the second metal lines.

Semiconductor device

A semiconductor device, includes: a substrate having a first surface on which a plurality of devices are disposed and a second surface, opposite to the first surface; an interlayer insulating film on the first surface of the substrate; an etching delay layer disposed in a region between the substrate and the interlayer insulating film; first and second landing pads on the interlayer insulating film; a first through electrode penetrating through the substrate and the interlayer insulating film; and a second through electrode penetrating the substrate, the etching delay layer, and the interlayer insulating film, the second through electrode having a width, greater than that of the first through electrode, wherein each of the first and second through electrodes includes first and second tapered end portions in the interlayer insulating film, each of first and second tapered end portions having a cross-sectional shape narrowing closer to the landing pads.

A semiconductor includes a substrate having a first surface and a second surface opposite to each other, the substrate having a via hole extending in a thickness direction from the first surface, a circuit pattern in the first surface of the substrate, a through electrode structure in the via hole, a device isolation structure in a first trench extending in one direction in the first surface of the substrate, the device isolation structure between the via hole and the circuit pattern, the device isolation structure including a first oxide layer pattern and a first nitride layer pattern sequentially stacked on an inner surface of the first trench, the first nitride layer pattern filling the first trench, and an insulation interlayer on the first surface of the substrate and covering the circuit pattern.

Through via electrode and device isolation structure including oxide layer pattern and nitride layer pattern sequentially stacked on inner surface of trench

A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

Semiconductor devices having bonding structures with bonding pads and metal patterns

A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.

Three-dimensional semiconductor memory device

Growing community of inventors

Yongin-si, South Korea

Hyoungyol Mun