Samsung Electronics Co., Ltd.

Hyoung-Young Lee

Jeong-Ho Bang

Hyun-Seop Shim

Ki-Bong Ju

Hyuk Jae Kwon

Young-Gu Shin

Hyuk Du Kwon

Kyoung-Il Heo

Sang-Do Han

Woo-Il Kim

Young-Ki Kwak

Sang-Go Han

A built-off test (BOT) device includes a signal processing block, an output selection block and a signal control block. The signal processing block duplicates a test signal to apply a plurality of duplicated test signals to each of a plurality of devices under test (DUTs) through each of corresponding channels, and the signal processing block provides a plurality of decision signals based upon a plurality of test result signals received from each of the DUTs. The output selection block merges the decision signals as a final decision signal or sequentially outputs the decision signals as the final decision signal, in response to an output mode selection signal. The signal control block provides the test signal to the signal processing block or provides the final decision signal externally, in response to a first switching control signal.

Built-off test device and test system including the same

A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Multichip package test

Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

Apparatus and method for performing parallel test on integrated circuit devices

Growing community of inventors

Kyunggi-do, South Korea

Hyoung-Young Lee