Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Hyoung Wook Lee

Woo Yong Sung

Jeong Ho Lee

Tae Woon Cha

Sang Gun Choi

Min-Su Kim

Min Su Kim

Jeongho Lee

Jihyun Bae

Sanggun Choi

Taewoon Cha

TaeGyun Kim

Rahul Singh

Dae Young Moon

Gun Ok Jung

Uk Rae Cho

The present invention relates to a liquid crystal display that maintains a more uniform cell gap and improves adherence between two display panels by improving adhesion between substrates and their bead spacers, as well as a manufacturing method thereof. An exemplary liquid crystal display includes: a first substrate and a second substrate facing each other; a bead spacer comprising a plurality of beads and a first adhesive coupling the beads to the first substrate; a second adhesive corresponding to the bead spacer and disposed on the second substrate so as to contact the bead spacer; and a liquid crystal layer disposed between the first substrate and the second substrate.

Liquid crystal display device and method for manufacturing thereof

Provided is a liquid crystal display including: a first substrate; a thin film transistor disposed on the first substrate; a passivation layer disposed on the thin film transistor and comprising a contact hole exposing an electrode of the thin film transistor; a pixel electrode disposed on the passivation layer and connected to the electrode of the thin film transistor through the contact hole; a lower buffer layer disposed on the pixel electrode; a lower alignment layer disposed on the lower buffer layer; a second substrate facing the first substrate; a common electrode disposed on the second substrate; an upper buffer layer disposed on the common electrode; and an upper alignment layer disposed on the upper buffer layer, in which the lower buffer layer comprises parylene, the upper buffer layer comprises parylene, or both the lower and the upper buffer layers comprise parylene.

Liquid crystal display and method for manufacturing the same

A clock-delayed domino logic circuit includes a first pre-charge circuit configured to pre-charge a first dynamic node with a pre-charge voltage in response to a first clock signal received via a first control terminal during a pre-charge operation; a first logic network configured to determine a logic level of the first dynamic node in response to first input data signals during an evaluation operation; and a first storage circuit which is connected between the first control terminal and the first dynamic node.

Clock-delayed domino logic circuit

A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.

Flip-flop and semiconductor device including the same

A display panel includes a first substrate, a second substrate facing the first substrate, and a pixel disposed on either the first substrate or the second substrate. When an electrode is formed, a portion of the electrode is removed to form a spacer area and a droplet including a bead spacer mixed with a solvent is provided in the spacer area. Then, the solvent is vaporized to move the bead spacer to a center of the spacer area. The second substrate is provided to face the first substrate while interposing the bead spacer therebetween. The spacer area has a dimension equal to or greater than a diameter of the droplet.

Display panel and method of manufacturing the same

A flip-flop circuit having a scan function includes an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the first input signal. The circuit includes a dynamic input unit to receive a second input signal, the scan enable signal, a first timing signal, and the internal timing signal, and to output a first output signal. The circuit also includes a static output unit to receive the first timing signal and the first output signal and to output a static output signal, and the dynamic input unit outputs the first output signal corresponding to one of the first input signal and the second input signal, respectively, based on a status of the scan enable signal.

Flip-flop circuit having scan function

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Seoul, South Korea

Hyoung Wook Lee