Samsung Electronics Co., Ltd.

Sungkyunkwan University

Hyoung-sub Kim

Dae-Ik Kim

Yoo-Sang Hwang

Ji-Young Kim

Sung-eui Kim

Byung-Lyul Park

Jae-Ho Kim

Hyeon-jin Shin

Chul-Sung Kim

Jung-Woo Park

Jang-yeon Kwon

Seong-jun Park

Kyoung-seok Son

Ja-hum Ku

Nak-jin Son

Ji-young Kim

Kyung Suh Park

Hoon Jeong

Jung-Min Ha

Sung-Kwan Choi

Seong-jun Jeong

Kang-hyun Lee

Hoo-jeong Lee

Mi-ran Moon

Yea-hyun Gu

Jong-seo Hong

Jae-hyun Yang

Min-seog Han

Example embodiments relate to a stacking structure having a material layer formed on a graphene layer, and a method of forming the material layer on the graphene layer. In the stacking structure, when the material layer is formed on the graphene layer by using an ALD method, an intermediate layer as a seed layer may be formed on the graphene layer by using a linear type precursor.

Stacking structure having material layer on graphene layer and method of forming material layer on graphene layer

A semiconductor device includes a substrate including an active region, a plurality of conductive line structures separate from the substrate, a plurality of contact plugs between the plurality of conductive line structures, a plurality of landing pads connected to a corresponding contact plug of the plurality of contact plugs, a landing pad insulation pattern between the plurality of landing pads, and a first insulation spacer between the landing pad insulation pattern and first conductive line structures from among the plurality of conductive line structures.

Semiconductor device including landing pad for connecting substrate and capacitor

A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.

Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices

Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction.

Method of manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.

Semiconductor device

Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.

A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and

Semiconductor devices and methods of manufacturing the same

Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.

Example embodiments relate to thin-film transistors (TFT) and methods for fabricating the same. A thin-film transistor according to example embodiments may include a gate, a gate insulation layer, a channel layer including a first oxide semiconductor layer and a second oxide semiconductor layer, and a source and drain on opposite sides of the channel layer. The first oxide semiconductor layer may have relatively large crystal grains compared to the second oxide semiconductor layer.

Thin-film transistor and method of manufacturing the same

An integrated circuit transistor includes an active region in a substrate, elongated along a first direction. A gate pattern is disposed on the substrate and crosses the active region along a second direction transverse to the first direction. The gate pattern includes an access gate portion disposed on the active region and narrowed at a central portion thereof. The gate pattern may further include a pass gate portion adjoining the access gate portion at the point beyond the edge of the active region, the pass gate portion having a lesser extent along the first direction than the access gate portion.

Transistor structures having access gates with narrowed central portions

A reverse self-aligned field effect transistor and a method of fabricating the same are provided. The reverse self-aligned transistor includes a source formed on an active region of a semiconductor substrate and a drain formed on the active region of the semiconductor substrate, the drain being positioned a predetermined distance from the source. A silicide film is formed on the source and the drain. Insulative film spacers are formed on sidewalls of a trench, the trench being formed by etchin the semiconductor substrate between the source and the drain. A gate insulative film is formed on a lower portion of the trench and a metal gate is formed on the gate insulative film between the insulative film spacers. The metal gate is electrically isolated from the source and the drain by the insulative film spacers.

Transistor having reverse self-aligned structure

A method of manufacturing a metal wiring layer in a semiconductor device, wherein an insulating layer is plasma treated before a tungsten nitride film is formed on the insulating layer. A metal, metal silicide or metal alloy thereafter being deposited over the tungsten nitride film.

Method of manufacturing a wiring layer in semiconductor device

Methods of forming semiconductor substrates having inverted-trench isolation regions therein include the steps of forming at least one trench in a semiconductor substrate at a first face thereof and then forming a stopping layer on the bottom of the trench. An etching or polishing step is then performed on a second face of the substrate which extends opposite the first face, until the stopping layer is exposed. Semiconductor devices are then formed in the remaining portions of the substrate extending adjacent sidewalls of the trench, at the polished second face. In particular, first and second trenches are preferably formed at a first face of a first semiconductor substrate and then respective first and second stopping layers comprising silicon nitride are formed on bottoms of the first and second trenches. First and second electrically insulating layers (e.g., SiO.sub.2) are then formed on the first and second stopping layers, to fill the first and second trenches. The electrically insulating layers are then polished using a chemical-mechanical polishing step to form a substantially planar surface to which a second substrate is preferably bonded. A second face of the first substrate, extending opposite the first face, is then polished until the stopping layers are exposed and a smooth semiconductor surface is defined extending between the first and second trenches. Semiconductor devices are then formed in the substrate, opposite the smooth semiconductor surface and between the insulation-filled trenches.

Methods of forming semiconductor devices in substrates having

A semiconductor device, e.g., a DRAM, having vertical conduction transistors and cylindrical cell gates, which includes a plurality of spaced-apart trench isolation regions formed in a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a silicon pillar formed on each bit line, a gate insulating layer and gate line formed on each silicon pillar in surrounding relationship thereto, a planarizing layer formed in recesses in the gate lines, an insulating layer formed on the upper surfaces of the gate line and planarizing layer, a plurality of contact holes provided in vertically aligned portions of the insulating layer, the gate line, and the gate insulating layer located above respective ones of the silicon pillars, and, a storage node of a capacitor formed with the contact holes and adjacent surface portions of the insulating layer, in contact with the source region of respective ones of the silicon pillars. Each of the silicon pillars includes vertically stacked layers which serve as respective drain, channel, and source regions of a transistor.

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Seongnam-si, South Korea

Hyoung-sub Kim