Hynix Semiconductor Inc.

Skhynix Inc.

Hyoung Soon Yune

Joo Kyoung Song

Tae Kyung Kim

Chul Young Park

Joo Hong Jeong

Do Youn Kim

Dong Sook Chang

Hak Yong Sim

Yeong Bae Ahn

A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.

Semiconductor device and method of manufacturing the same

A semiconductor device may be provided. The semiconductor device may include conductive patterns surrounding a channel film. The conductive patterns may be stacked and spaced apart from one another. The semiconductor device may include a gate contact plug coupled to one of the conductive patterns. The semiconductor device may include support pillars penetrating the conductive patterns in a periphery of the gate contact plug.

Semiconductor device

The present disclosure may provide a semiconductor device with an enhanced integration. The device may include a lower pipe gate; an upper pipe gate including a first horizontal portion and first and second protrusions, the first horizontal portion being parallel to the lower pipe gate, the first and second protrusions extending from the first horizontal portion to the lower pipe gate and crossing each other so as to define a pipe channel region; a partition pipe gate disposed between the lower and upper pipe gates, the partition pipe gate dividing the pipe channel region into first and second pipe channel regions; and first and second pipe channel films disposed respectively in the first and second pipe channel regions.

A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.

Buried word line and connection pad for memory device

Forming a buried word line and connection pad for memory apparatus

A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device.

Exposure mask and method for manufacturing semiconductor device using the same

A semiconductor device including a CMP dummy pattern and a method for manufacturing the same are provided. The warpage of a wafer can be prevented by forming the CMP dummy pattern in the same direction and/or at the same angle as a pattern of a cell region. Accordingly, overlay error caused by etching residues is reduced, thereby improving the yield of the semiconductor device.

Semiconductor device having CMP dummy pattern

A method for manufacturing a semiconductor device which includes fine patterns having various critical dimensions (CDs) by adjusting a thickness of spacer used as an etching mask in Spacer Patterning Technology (SPT). The method for manufacturing a semiconductor device includes forming spacers at a different level over an etching target layer and etching the etching target layer exposed among the spacers.

Method for manufacturing semiconductor device

A method for processing optical proximity correction is disclosed which eliminates a need for repeated implementation of experiments and result in a reducing the processing time as compared to trial and error. Furthermore, the method can realize an optimal insertion of the assist pattern by applying different conditions to specific layers. The method includes determining whether or not to insert an assist pattern around an outermost pattern. A shape of the assist pattern inserted around the outermost pattern is determined. The contrast of the outermost pattern is compared against a contrast of a cell array pattern. The contrast of the outermost pattern is repeated compared with the contrast of the cell array pattern under a defocus state.

Standardization of assist pattern inserted into outermost pattern for enhancing depth of focus margin

A method for forming a fine contact hole of a semiconductor device comprises performing two-step etching processes using a first exposure mask including a plurality of rectangular light transmitting regions each having a given pitch and a second exposure mask including a plurality of rectangular light transmitting regions arranged a shielding region of the first exposure mask with a 'cross (+)' shape in the center of rectangular light transmitting regions of the second exposure mask. Each of four corner regions of the light transmitting regions of the first exposure mask is overlapped with four corner regions of rectangular light transmitting regions of the second exposure mask. As a result, the fine contact hole pattern obtained by the method has a uniform size.

Method for forming fine contact hole pattern of semiconductor device

A method of fabricating patterns of a semiconductor device includes the steps of forming first sacrificial layer patterns over a pattern target layer; forming first spacers on sidewalls of the first sacrificial layer patterns; forming a second sacrificial layer pattern over the first sacrificial layer patterns and the first spacers such that at least one of the first spacers is exposed by the second sacrificial layer pattern; forming a dual spacer by forming a second spacer on the exposed first spacer; removing the second sacrificial layer pattern and the first sacrificial layer patterns; and forming a first pattern having a first pitch defined by the first spacers and a second pattern having a second pitch defined by the dual spacer by etching an exposed portion of the pattern target layer using the first spacers and the dual spacer as etching masks.

Method of fabricating pattern in semiconductor device using spacer

A semiconductor device having an improved gate process margin includes two active regions spaced apart from each other on a semiconductor substrate and respectively having bent sides with recesses and protrusions corresponding to each other, and two line-shaped gate patterns respectively formed in the longitudinal directions of the active regions. A gap at which the two gate patterns are spaced apart from each other by the recesses and the protrusions in the active regions is relatively narrower by a width difference between the recesses and the protrusions.

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Seoul, South Korea

Hyoung Soon Yune