Magnachip Semiconductor, Inc.

Magnachip Mixed-signal, Ltd.

Hyoung Kyu Kim

Dae Young Yoo

Yeon Kyoung Park

Jun Sik Min

Tae Kyoung Kang

Jin Seok Yang

Eun Kyu Seong

Hyung Sun Kim

Ju Sang Park

Jin Seop Noh

Il Jun Kim

Kwon Young Oh

Sang Ho Lee

Won Seok Lee

A power source switching circuit for a memory device includes: a first power source voltage terminal for supplying a first power source voltage, a second power source voltage terminal for supplying a second power source voltage, a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET connected in series with the first power source voltage terminal, a first level shifter connected to the first MOSFET and supplied with the first power source voltage, a second level shifter connected to the second MOSFET and supplied with the second power source voltage, a third MOSFET connected to the second MOSFET, and a third level shifter connected to the third MOSFET and supplied with a third power source voltage, and a memory cell of a non-volatile memory is programmed using the first power source voltage or the second power source voltage.

Power source switching circuit for memory device

A current generating circuit includes a current generator configured to supply a reference current, switches connected to the current generator, wherein one switch of the switches is selected and configured to operate, according to a switch selection signal, and one or more resistors, respectively connected to the switches, wherein a rate of current change according to a temperature change of the current generator is adjusted based on a temperature coefficient of resistance (TCR) of resistors connected to the one switch, according to adjustment of the one switch.

Current generating circuit and oscillator using current generating circuit

A low dropout voltage regulator includes a differential amplifier configured to output an amplified voltage by comparing a feedback voltage with a reference voltage, a pass transistor configured to receive a power input voltage into a source terminal, the amplified voltage into a gate terminal, and output an output voltage into a drain terminal, distribution resistors connected between the drain terminal and the ground terminal, configured to generate the feedback voltage, and an inrush preventer, connected in parallel between the differential amplifier and the pass transistor, and configured to output a regulated amplified voltage into the gate terminal according to a control signal, wherein the inrush preventer comprises a determiner configured to output an enable signal that is turned on during an initial driving period, and a limiter configured to output the regulated amplified voltage according to the enable signal.

Low dropout voltage regulator and driving method of low dropout voltage regulator

A panel control circuit configured to control a display panel includes a plurality of pixels. The panel control circuit includes a controller configured to output an image data and a source driver, including an output circuit and an output control circuit, configured to generate data signals based on the image data. The controller is configured to output an output change signal for changing an output of the source driver. The output circuit is configured to output the data signals to the display panel, and the output control circuit is configured to output an adjusting current to the output circuit in a signal transition section of the output change signal.

Panel control circuit and display device including the same

A driving device of a flat panel display configured to receive an image signal and a clock signal includes a driving circuit configured to convert the image signal into pixel data and output the pixel data, a timing controller configured to generate and output a vertical synchronization signal, a horizontal synchronization signal, a source change enable signal, and a display enable signal using the image signal and the clock signal, an output buffer including an input terminal configured to receive the pixel data and an output terminal connected to the flat panel display, and a buffer controller connected to the timing controller and the output buffer and configured to control a bias current, applied to the output buffer, to be decreased by a value during a period.

Driving device of flat panel display and driving method thereof

A display driving device for driving a display panel includes a first driving circuit configured to output a first image signal, a second driving circuit configured to output a second image signal, a first switch circuit connected to the first driving circuit, and configured to transmit the first image signal to a part of a first set of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval, and a second switch circuit connected to the second driving circuit, and configured to transmit the second image signal to a part of a second set of sub-pixels arranged in the display panel adjacent to the first set of sub-pixels based on a second switching signal during the first horizontal time interval, wherein a width of the first switching signal and a width of the second switching signal in the first horizontal time differ from each other.

Display driving device and display device including the same

A control buffer in a source driver includes a first CMOS inverter configured to output a switch signal to control turning on and off of a switch, and a first tri-state inverter that is connected to the first CMOS inverter and configured to selectively adjust a size of the control buffer, wherein a slew rate of the switch signal is adjusted depending on the size of the control buffer.

Control buffer for reducing EMI and source driver including the same

A source driver apparatus for a display panel includes source drivers and a slew rate controller. Each of the source drivers includes a data latch, a decoder, and an output buffer. The data latch is configured to hold sub-pixel data. The decoder is configured to decode the sub-pixel data held in the data latch to provide a driving signal. The output buffer has an adjustable slew rate and is configured to buffer the driving signal to provide a buffered driving signal. The slew rate controller is configured to analyze the sub-pixel data in the data latch in each of the source drivers and dynamically control the slew rate of the output buffer in each of the source drivers.

Source driver unit for a display panel

There is provided a current controlling mode DC-DC converter that operates in a PWM mode or a PFM mode by adjusting a turned-on time of a gate depending on power consumption of a load. The DC-DC converter includes a first comparator that receives a first input voltage and a second input voltage and outputs a first output signal, a second comparator that receives a reference voltage for mode switching and the second input voltage and outputs a second output signal, and a first logic element that outputs a reset signal for turning off a gate at a point of time when both the first output signal and the second output signal are applied. Examples may also include additional elements to facilitate mode switching.

Current controlling mode direct current (DC)-DC converter

Provided are a ramp circuit and a DC-DC converter. The ramp circuit generates a current flowing in a resistor using voltages affected by an output voltage and an input voltage of a DC-DC converter, and generates a ramp signal through copying of the current and charging and discharging of a capacitor using a current mirror unit. The ramp signal is generated by considering the input voltage and the output voltage, and thus the ramp signal has an optimal slope to provide an adaptive response to state change in the input voltage and the output voltage. The DC-DC converter uses such a ramp circuit to facilitate its operation.

Growing community of inventors

Cheongju-si, South Korea

Hyoung Kyu Kim