Samsung Electronics Co., Ltd.

Hyoung-Joon Kim

Byeong-Yun Nam

Byeong-yun Nam

Gwan-Hyeob Koh

Su-Jin Ahn

Beom-jun Jin

Young-Wook Park

Young-pil Kim

Kyung-won Park

Dong-Hyun Kim

Sang-Woo Lee

Jun-Jin Kong

Hak-soo Yu

Joo-Young Hwang

Hyeong-Geun An

Chang-woong Chu

Yong-chul Oh

Ji-soo Kim

In-Su Choi

Sang-Hyeop Lee

A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.

Device including an external memory connection unit capable of adopting an external memory

Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.

Methods of fabricating semiconductor devices with scalable two transistor memory cells

Ferroelectric capacitors include a support insulating film on an integrated circuit substrate and having a trench therein. A lower electrode is on sidewalls and a bottom surface of the trench. A seed conductive film covers the lower electrode. A ferroelectric film is provided on the support insulating film and the seed conductive film and an upper electrode is provided on the ferroelectric film. The lower electrode may fill the trench and the ferroelectric film may extend over all of the seed conductive film and the support insulating film adjacent the seed conductive film.

Ferroelectric capacitors including a seed conductive film

An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad and integrated circuit devices formed thereby

The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Methods of fabricating integrated circuit devices providing improved short prevention

Semiconductor devices with scalable two transistor memory cells

Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad

The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

Integrated circuit devices providing improved short prevention

Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

Methods for forming conductive contact body for integrated circuits using dummy dielectric layer

A half-tone phase shift mask includes a transparent substrate, a phase shift pattern formed on the semiconductor substrate and having a stepped aperture which exposes the transparent substrate by a predetermined width, and an opaque film pattern formed on the upper surface of the phase shift pattern. The stepped aperture is defined by an interior side wall of the phase shift pattern. This side wall includes a horizontal surface which is parallel to the surface defining the bottom of the aperture. Light transmitted by the mask via the surface defining the bottom of the aperture has a phase difference of 180 degrees with respect to light transmitted by the mask via the horizontal surface, and light transmitted by the mask via the surface defining the bottom of the aperture has a phase difference of more than 180 degrees with respect to light transmitted by the mask via the upper surface of the phase shift pattern. Accordingly, the half-tone phase shift mask includes a first transmissive region for blocking light, a second transmissive region that sets the width of a pattern to be formed on photosensitive film, a third transmissive region for causing light transmitted thereby to be out of phase by 180 degrees with respect to the light transmitted by the second transmissive region, and a fourth transmissive region having a width greater than the width of the third transmissive region for causing light transmitted thereby to be out of phase by more than 180 degrees with respect to light transmitted by the second transmissive region.

Half-tone phase shift mask having a stepped aperture

A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.

Method for forming conductive contact of semiconductor device

Half-tone phase shift masks (PSM) having a high transmittance and can be easy to fabricate are provided. The half-tone PSM includes a substrate which is transparent with respect to exposure light, a phase shifter pattern formed on the transparent substrate, and a phase shifting groove which can be formed by etching the transparent substrate. Methods for fabricating half-tone PSMs are also provided. The half-tone PSM can have a higher transmittance than that of a conventional half-tone PSM, and the phase shifting groove can have a uniform surface. Thus, a fine pattern having an excellent contrast can be formed using a short wavelength.

Growing community of inventors

Seoul, South Korea

Hyoung-Joon Kim