Samsung Electronics Co., Ltd.

Hyonwook Ra

Jongchul Park

Deokhan Bae

Juhun Park

Hyung Jong Lee

A wafer processing apparatus is provided. The wafer processing apparatus includes a chamber body defining a plasma region configured that plasma is generated in the plasma region, a wafer support arranged in the chamber body and configured to support a wafer, first and second electrodes arranged between the wafer support and the plasma region and having apertures configured to guide a path of ions of the plasma, a first power source configured to apply, to the first electrode, a voltage that is higher than a voltage applied to the second electrode, and a second power source configured to apply, to the wafer support, a voltage that is higher than the voltage applied to the second electrode.

Wafer processing apparatus

A semiconductor device includes a substrate including active patterns, a device isolation layer filling a trench between a pair of adjacent active patterns, a gate electrode on the active patterns, and a gate contact on the gate electrode. Each active pattern includes source/drain patterns at opposite sides of the gate electrode. The gate contact includes a first portion vertically overlapping with the gate electrode, and a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode. A bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion. The bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern that is adjacent to the second portion.

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Hwaseong-si, South Korea

Hyonwook Ra