Samsung Electronics Co., Ltd.

Hyongsoo Kim

Jong-Min Lee

Jongryul Jun

Eunkee Hong

Mansug Kang

Dongkyun Park

Kyungmun Byun

Sangjun Park

Joon Hyuk Kim

Jin-Su Lee

Jinah Kim

Kukhan Yoon

Kwangtae Hwang

Young-Seok Choi

Siwoo Kim

Jiseung Lee

WonSeok Yoo

Eunsuk Choi

Yeram Kim

Seonbaek Lee

Hojun Kwon

A semiconductor device may include an active pattern, a capacitor contact structure electrically connected to the active pattern, and a capacitor structure electrically connected to the capacitor contact structure. The capacitor structure may include a first lower electrode and a second lower electrode that are adjacent to each other, a supporter supporting the first and second lower electrodes, a capacitor insulating layer covering the first and second lower electrodes, and an upper electrode on the capacitor insulating layer. The supporter may include a first supporter curved sidewall connected to the first lower electrode and the second lower electrode, and the upper electrode may include an intervening electrode portion enclosed by the supporter. The first supporter curved sidewall may be convex toward the intervening electrode portion.

Semiconductor device and method of fabricating the same

A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Capacitor structure and semiconductor device including the same

A method of fabricating a semiconductor device includes forming an etch-target layer on a substrate having an alignment key, forming a transparent first pattern on the etch-target layer to face the alignment key, forming an opaque second pattern on the etch-target layer to be adjacent to the first pattern, and etching the etch-target layer using the first pattern and the second pattern as an etch mask.

Methods of fabricating a semiconductor device

Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes.

Capacitor of semiconductor device and method of fabricating the same

A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern.

Semiconductor memory devices including support patterns

An integrated circuit device with capacitors and methods of forming the integrated circuit device are provided. The methods may include forming a first lower capacitor electrode pattern on an inner surface of a hole in a mold layer. The first lower capacitor electrode pattern may have a hollow cylindrical shape and an opening in an upper surface. The method may further include forming a second lower capacitor electrode pattern plugging the opening and an upper surface of the second lower capacitor electrode pattern may be planar. The first and the second lower capacitor electrode patterns may comprise a lower capacitor electrode including a void. Additionally, the method may include removing the mold layer to expose the lower capacitor electrode, forming a dielectric layer on the lower capacitor electrode, and forming an upper capacitor electrode layer on the dielectric layer.

Integrated circuit devices with capacitor and methods of manufacturing the same

Methods of fabricating semiconductor memory devices including support patterns

A semiconductor memory device includes at least one supporting pattern on a substrate, a storage node penetrating the supporting pattern, an electrode layer disposed around the storage node and the supporting pattern, and a capacitor dielectric interposed between the storage node and the electrode layer. The supporting pattern includes germanium oxide.

Semiconductor memory devices and methods of fabricating the same

Growing community of inventors

Hwaseong-si, South Korea

Hyongsoo Kim