Samsung Electronics Co., Ltd.

Hyongryol Hwang

Taeyoung Oh

Jongcheol Kim

Kyungho Lee

Kiheung Kim

Daehyun Kim

Kyungryun Kim

Minho Choi

Hohyun Shin

Ki-Heung Kim

Sanghoon Jung

Wonil Bae

Jaeseong Lim

Kijun Lee

Sunghye Cho

Myungkyu Lee

Kyomin Sohn

Kyung-ho Lee

Jinseong Yun

Seongmuk Kang

Yoonjae Jeong

A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.

Memory module for performing one-time programmable (OTP) addressing operation to store unique ID of each memory device in an ID storge region of each memory device, and storage device including the same

A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.

Semiconductor memory device and memory system including the same

A memory device includes an ECC circuit that performs error correction code (ECC) encoding on input data to generate write data, and a memory cell array including a plurality of memory cells that stores the write data. The ECC circuit includes a data splitter that splits the input data into first sub-data and second sub-data, a first ECC encoder that performs ECC encoding on the first sub-data to generate first sub-parity data, a second ECC encoder that performs ECC encoding on the second sub-data to generate second sub-parity data, and a data scrambler that performs a data scrambling operation with respect to the first sub-data, the second sub-data, the first sub-parity data, and the second sub-parity data based on a structure of the memory cell array to generate the write data.

Memory device and operation method thereof

A semiconductor memory device includes a plurality of memory cells partitioned into a plurality of row blocks that are each associated with at least one respective row block identity bit within a portion of a row address. A row decoder is provided, which includes a repair controller having a plurality of fuse boxes therein that correspond to respective ones of the plurality of row blocks and include a first fuse box configured to store a first defective address. The repair controller is configured to: (i) activate a first redundancy word-line, which replaces a first defective word-line designated by the first defective address, in response to comparing a first access address with the first defective address output from the first fuse box, during a first mode, and (ii) activate a second redundancy word-line, which replaces a first edge word-line designated by the first access address, in response to comparing the first access address with a first reset address output from the first fuse box, during a second mode.

Semiconductor memory device and method of operating semiconductor memory device

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.

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Seoul, South Korea

Hyongryol Hwang