Samsung Electronics Co., Ltd.

Hyon-chol Kim

Heung-Kyu Kwon

Su-Chang Lee

Seok-Won Lee

Chi-young Lee

Jung-Hwan Kim

Tae-Hong Min

Jae-Wook Yoo

Yun-Hyeok Im

Kwang-Chul Choi

Min-Ok Na

Ji-hwan Hwang

Chung-sun Lee

Eun-kyoung Choi

A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.

Semiconductor packages having warpage compensation

A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.

Stack packages having fastening element and halogen-free inter-package connector

A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

Stack package and semiconductor package including the same

Growing community of inventors

Hwaseong-si, South Korea

Hyon-chol Kim