Samsung Electronics Co., Ltd.

Hyok-Ki Kwon

Jeong-Uk Han

Yong-Suk Choi

Hee-Seog Jeon

Sung-Taeg Kang

Seung-Jin Yang

Seung Beom Yoon

Hee Seog Jeon

Yong-Tae Kim

Ki-chul Kim

Young-cheon Jeong

Bo Young Seo

Chang-Hun Lee

Yong Tae Kim

Bo-Young Seo

Bae-Seong Kwon

Hong-kook Min

BoYoung Seo

A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.

Semiconductor memory devices having a floating gate with a projecting portion and methods of forming semiconductor memory devices having a floating gate with a projecting portion

a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

Nonvolatile memory device and method of fabricating the same

A semiconductor device includes a first transistor and a second transistor formed on a substrate. Each of the first transistor and the second transistor has a first source region, first drain region of a first conductivity type and a gate. The first transistor is an off-transistor and includes a second source/drain region of the first conductivity type which surrounds at least a portion of the first source/drain region in the first transistor.

Semiconductor device and methods for forming the same

Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Split gate non-volatile memory devices and methods of forming the same

A non-volatile memory device includes isolation layers, a cell trench, a floating gate, a common source region and a word line. The isolation layers define an active region of a substrate. The cell trench is formed in the active region. The cell trench extends in a first direction. The floating gate is formed on the active region and in the cell trench. The common source region is formed on the active region adjacent a second side face of the floating gate and extends in a second direction substantially perpendicular to the first direction. The word line is formed on the active region, which is adjacent to a first side face of the floating gate opposite to the second side face, and the isolation layers and in the cell trench. The word line extends in the second direction.

Non-volatile memory device and method of manufacturing the same

A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.

Nonvolatile memory devices and methods of fabricating the same

A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.

Semiconductor flash memory device and method of fabricating the same

A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench. An inter-gate insulating layer is formed on the upper portion of floating gate and interposed between the floating gate and the control gate, and a drain region is formed in the surface of the substrate adjacent the control gate and spaced from the second sidewall of the trench.

Growing community of inventors

Yongin-si, South Korea

Hyok-Ki Kwon