Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Hyojin Choi

Yongsoo Lee

Jaekyung Yang

Seongho Son

Chulwoo Park

Younsik Park

Haksoo Yu

Jaeyoun Youn

Sung Hyun Lee

Uksong Kang

Jun Hee Yoo

Changwook Jeong

In Huh

Sua Kim

Dongsoo Kang

Taewoong Kong

Seungju Kim

Jun Haeng Lee

Hak-soo Yu

Dae-hyun Kim

Chaseung Jun

Jinwoo Park

Younghwan Kwack

Yongwoo Lee

Hyeongtae Kim

Sangchul Han

Joosun Choi

Youngmin Oh

Jeonghoon Ko

Sangju Lee

Hyun Sun Park

Jaecheol Lee

Jinsu Jung

Joonwan Chai

Jaewon Ko

Hyeonsik Son

The present disclosure relates to a power converting device and a home appliance including the same. A power converting device according to an embodiment of the present disclosure comprises a first capacitor, a first switching element turned on to output a first voltage stored in the first capacitor to a first node which is one end of an inductive load, a second switching element, one end of which is connected to the first switching element and which is turned on to decrease the voltage of the first node to the first voltage, a third switching element turned on to output a second voltage greater than the first voltage to the first node which is one end of the inductive load, and a fourth switching element, one end of which is connected to the third switching element and which is turned on to decrease the voltage of the first node to the ground voltage. Accordingly, switching loss may be reduced when power is supplied to an inductive load.

Power converting device and home appliance including the same

A system verification method includes generating a first verification vector as a result of a first action of an agent, the first verification vector referring to an observation corresponding to at least one state already covered, from among states of elements of a target system, identifying a first coverage corresponding to at least one state covered by the first verification vector, from among the states of the elements, updating the observation by reflecting the first coverage in the observation, and generating a second verification vector through a second action of the agent, the second verification vector referring to the updated observation.

Method and apparatus with system verification based on reinforcement learning

An induction heat cooking apparatus includes a rectifier configured to convert an AC voltage supplied from a power source into a DC voltage, a battery configured to store power, a switch configured to connect to at least one of the rectifier or the battery, an inverter connected to the switch and configured to receive a first voltage from at least one of the rectifier or the battery and convert the first voltage to a second voltage, and a heating coil configured to receive the second voltage from the inverter and generate magnetic fields in which the heating coil is configured to heat a cooking device based on the generated magnetic fields.

Induction heat cooking apparatus and method for operating the same

An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

Electronic devices generating verification vector for verifying semiconductor circuit and methods of operating the same

A memory device including: a memory cell array including a plurality of memory cell rows; an address buffer configured to store addresses of target rows of the plurality of memory cell rows, wherein the addresses of the target rows have been repeatedly accessed; a minimum access output circuit configured to select, when there are a plurality of rows having a same minimum access count among the target rows, any one of the plurality of rows having the same minimum access count as a minimum access row based on a selection command value, and to output an index value of the minimum access row; and a control circuit configured to output a command instructing replacement of an address corresponding to the index value of the minimum access row with an address of an access row and storage of the address of the access row in the address buffer.

Memory device for processing a row-hammer refresh operation and a method of operating thereof

An induction heating device includes: a casing; a cover plate coupled to a top of the casing, where the cover plate has a surface configured to seat an object; a first induction heating module located within the casing and configured to heat the object; a first wiring substrate that is configured to couple to a bottom of the first induction heating module and that extends in a first direction, where the first wiring substrate includes at least one of a power line or a signal line; and a first connector that is configured to couple the first wiring substrate to the bottom of the first induction heating module, where the first connector includes a pogo pin.

Induction heating device having reduced number of wire harnesses

Disclosed herein is an induction heat cooking apparatus including a power supply configured to supply an alternating current (AC) voltage, a rectifier configured to rectify the supplied AC voltage into a direct current (DC) voltage, first and second switching units configured to control switching such that the DC voltage from the rectifier is alternately applied to a working coil, a comparison unit configured to sense current flowing in the working coil and to compare the sensed current with a predetermined reference value to output pulses, and a controller configured to determine whether a cooking vessel is present on the working coil based on the output pulses.

Induction heat cooking apparatus and operating method thereof

A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

Test method of semiconductor memory device and semiconductor memory system transferring fail address data from a volatile to a non-volatile memory array using an error-correction code engine

A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.

DRAM controller having DRAM bad page management function and bad page management method thereof

A semiconductor memory cell array is provided which includes a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed. The first and second memory cell array areas are accessed by addressing of a DRAM controller.

Semiconductor memory cell array having fast array area and semiconductor memory including the same

A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.

Semiconductor memory device with operation functions to be used during a modified read or write mode

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Seoul, South Korea

Hyojin Choi