Yc Corporation

Hyo Sang Jo

Yong Hyun Kim

Jae Hoon Joo

Wan Soon Park

Ki Young Jeon

A semiconductor test apparatus is provided. The semiconductor test apparatus includes: a test management unit determining a test mode, generating a test signal in accordance with the determined test mode, and transmitting the test signal to fail memories; and one or more fail memory boards including the fail memory, which store fail signals generated as a result of a test conducted in accordance with the test signal and address information of the fail signals, wherein if the determined test mode is a first test mode, at least some of the failure memory boards are powered off.

Semiconductor test apparatus capable of inducing reduction of power consumption

A semiconductor wafer test system for controlling the supply of power to a semiconductor wafer test apparatus is provided. The semiconductor wafer test system includes a test operating server and the semiconductor wafer test apparatus. The test operating server manages a wafer test schedule and allocates lots to a prober, which loads wafers into the semiconductor wafer test apparatus, in accordance with the wafer test schedule. The test operating server sends a mode switch request to the semiconductor wafer test apparatus in accordance with the wafer test schedule, and the semiconductor wafer test apparatus is switched to a waiting mode in response to receipt of a request to switch to the waiting mode from the test operating server, and is switched to a ready mode in response to receipt of a request to switch to the ready mode from the test operating server.

Semiconductor wafer test system for controlling supply of power to semiconductor wafer test apparatus and method of controlling supply of power to semiconductor wafer test apparatus

Growing community of inventors

Uiwang-si, South Korea

Hyo Sang Jo