Samsung Electronics Co., Ltd.

Hyo Joon Ryu

Jee Hoon Han

Kohji Kanamori

Seo-Goo Kang

Young Hwan Son

Jung Hoon Jun

Sang Youn Jo

Hee Suk Kim

Jong Seon Ahn

Jeong Yong Sung

A semiconductor memory device includes a lower stacked structure with lower metal lines on a substrate, an upper stacked structure with an upper metal line on the lower stacked structure, a vertical structure penetrating the upper and lower stacked structures and including a channel layer, a first cutting line through the upper and lower stacked structures, an upper supporter in a recess on the first cutting line, a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line, a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first and second cutting lines, top surfaces of the upper supporter and sub-cutting line being coplanar, and a first interlayer insulating layer surrounding a sidewall of each of the upper supporter and the sub-cutting line.

Memory device with vertically stacked semiconductor structures

A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

Semiconductor memory device and method of fabricating the same

A semiconductor memory device includes; a lower stacked structure including lower metallic lines stacked in a first direction on a substrate, an upper stacked structure including a first upper metallic line and a second upper metallic line sequentially stacked on the lower stacked structure, a vertical structure penetrating the upper stacked structure and lower stacked structure and including a channel film, a connection pad disposed on the vertical structure, contacted with the channel film and doped with N-type impurities, a first cutting line cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, a second cutting line spaced apart from the first cutting line in a second direction different from the first direction, and cutting the lower metallic lines, the first upper metallic line and the second upper metallic line, and sub-cutting lines cutting the first upper metallic line and the second upper metallic line between the first cutting line and the second cutting line. The channel film includes an undoped channel region and a doping channel region, and the doping channel region contacts the connection pad and overlaps a part of the second upper metallic line in the second direction.

3D semiconductor memory device and method of fabricating same

Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.

Nonvolatile memory device and method for fabricating the same

A semiconductor memory device includes a mold structure including a plurality of wordlines on a front side of a first substrate, and a string selection line and a stopper line on the plurality of wordlines. A channel structure extends in a vertical direction to penetrate the mold structure. A block separation area extends in a first direction to cut the mold structure. A protective structure is interposed between the block separation area and the stopper line and not between the block separation area and the string selection line and not between the block separation area and the plurality of wordlines. A string separation structure extends in the first direction to cut the string selection line and the stopper line. A bitline extends in a second direction on the mold structure. A bitline contact connects the channel structure and the bitline.

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Hwaseong-si, South Korea

Hyo Joon Ryu